Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	254	1		T16	4		T12	4		T13	7
all_values[1]	254	1		T16	4		T12	4		T13	7
all_values[2]	254	1		T16	4		T12	4		T13	7
all_values[3]	254	1		T16	4		T12	4		T13	7
all_values[4]	254	1		T16	4		T12	4		T13	7
all_values[5]	254	1		T16	4		T12	4		T13	7
all_values[6]	254	1		T16	4		T12	4		T13	7
all_values[7]	254	1		T16	4		T12	4		T13	7
all_values[8]	254	1		T16	4		T12	4		T13	7
all_values[9]	254	1		T16	4		T12	4		T13	7
all_values[10]	254	1		T16	4		T12	4		T13	7
all_values[11]	254	1		T16	4		T12	4		T13	7
all_values[12]	254	1		T16	4		T12	4		T13	7
all_values[13]	254	1		T16	4		T12	4		T13	7
all_values[14]	254	1		T16	4		T12	4		T13	7
all_values[15]	254	1		T16	4		T12	4		T13	7
all_values[16]	254	1		T16	4		T12	4		T13	7
all_values[17]	254	1		T16	4		T12	4		T13	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6040	1		T16	101		T12	86		T13	149
auto[1]	2088	1		T16	27		T12	42		T13	75

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5592	1		T16	87		T12	84		T13	162
auto[1]	2536	1		T16	41		T12	44		T13	62

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4817	1		T16	79		T12	81		T13	127
auto[1]	3311	1		T16	49		T12	47		T13	97

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	77	1		T16	2		T13	1		T14	1
all_values[0]	auto[0]	auto[1]	auto[0]	77	1		T16	1		T12	3		T13	5
all_values[0]	auto[1]	auto[0]	auto[1]	53	1		T16	1		T15	2		T59	2
all_values[0]	auto[1]	auto[1]	auto[1]	47	1		T12	1		T13	1		T14	2
all_values[1]	auto[0]	auto[0]	auto[0]	74	1		T16	2		T13	2		T14	4
all_values[1]	auto[0]	auto[1]	auto[0]	75	1		T12	3		T13	1		T59	3
all_values[1]	auto[1]	auto[0]	auto[1]	53	1		T16	2		T13	1		T15	2
all_values[1]	auto[1]	auto[1]	auto[1]	52	1		T12	1		T13	3		T59	1
all_values[2]	auto[0]	auto[0]	auto[0]	44	1		T16	2		T13	1		T15	1
all_values[2]	auto[0]	auto[0]	auto[1]	45	1		T16	1		T12	1		T14	1
all_values[2]	auto[0]	auto[1]	auto[0]	41	1		T13	3		T14	1		T59	2
all_values[2]	auto[0]	auto[1]	auto[1]	29	1		T12	2		T13	1		T59	1
all_values[2]	auto[1]	auto[0]	auto[1]	52	1		T16	1		T12	1		T13	2
all_values[2]	auto[1]	auto[1]	auto[1]	43	1		T59	1		T60	1		T61	3
all_values[3]	auto[0]	auto[0]	auto[0]	51	1		T16	1		T13	4		T14	4
all_values[3]	auto[0]	auto[0]	auto[1]	28	1		T15	1		T59	3		T62	1
all_values[3]	auto[0]	auto[1]	auto[0]	33	1		T16	1		T12	1		T13	1
all_values[3]	auto[0]	auto[1]	auto[1]	30	1		T16	1		T12	1		T59	1
all_values[3]	auto[1]	auto[0]	auto[1]	66	1		T13	1		T15	1		T59	3
all_values[3]	auto[1]	auto[1]	auto[1]	46	1		T16	1		T12	2		T13	1
all_values[4]	auto[0]	auto[0]	auto[0]	66	1		T12	2		T14	2		T15	2
all_values[4]	auto[0]	auto[0]	auto[1]	25	1		T13	1		T59	1		T61	1
all_values[4]	auto[0]	auto[1]	auto[0]	38	1		T12	1		T13	1		T14	1
all_values[4]	auto[0]	auto[1]	auto[1]	25	1		T16	2		T13	1		T15	1
all_values[4]	auto[1]	auto[0]	auto[1]	55	1		T16	1		T13	2		T14	1
all_values[4]	auto[1]	auto[1]	auto[1]	45	1		T16	1		T12	1		T13	2
all_values[5]	auto[0]	auto[0]	auto[0]	62	1		T16	1		T14	1		T59	1
all_values[5]	auto[0]	auto[0]	auto[1]	22	1		T16	1		T15	1		T61	2
all_values[5]	auto[0]	auto[1]	auto[0]	47	1		T13	5		T15	2		T59	2
all_values[5]	auto[0]	auto[1]	auto[1]	26	1		T12	3		T14	2		T59	2
all_values[5]	auto[1]	auto[0]	auto[1]	52	1		T16	2		T13	1		T15	1
all_values[5]	auto[1]	auto[1]	auto[1]	45	1		T12	1		T13	1		T14	1
all_values[6]	auto[0]	auto[0]	auto[0]	46	1		T16	1		T12	4		T59	1
all_values[6]	auto[0]	auto[0]	auto[1]	35	1		T16	1		T59	2		T60	1
all_values[6]	auto[0]	auto[1]	auto[0]	39	1		T13	2		T14	2		T15	2
all_values[6]	auto[0]	auto[1]	auto[1]	23	1		T15	1		T62	1		T63	1
all_values[6]	auto[1]	auto[0]	auto[1]	52	1		T16	1		T13	1		T14	1
all_values[6]	auto[1]	auto[1]	auto[1]	59	1		T16	1		T13	4		T14	1
all_values[7]	auto[0]	auto[0]	auto[0]	88	1		T16	1		T13	3		T14	1
all_values[7]	auto[0]	auto[1]	auto[0]	76	1		T12	1		T13	2		T14	2
all_values[7]	auto[1]	auto[0]	auto[1]	43	1		T16	3		T13	1		T15	1
all_values[7]	auto[1]	auto[1]	auto[1]	47	1		T12	3		T13	1		T14	1
all_values[8]	auto[0]	auto[0]	auto[0]	86	1		T16	1		T12	1		T13	2
all_values[8]	auto[0]	auto[1]	auto[0]	64	1		T16	1		T13	4		T14	1
all_values[8]	auto[1]	auto[0]	auto[1]	62	1		T12	1		T14	2		T59	2
all_values[8]	auto[1]	auto[1]	auto[1]	42	1		T16	2		T12	2		T13	1
all_values[9]	auto[0]	auto[0]	auto[0]	43	1		T14	1		T15	1		T59	2
all_values[9]	auto[0]	auto[0]	auto[1]	32	1		T16	2		T12	1		T15	1
all_values[9]	auto[0]	auto[1]	auto[0]	44	1		T13	2		T59	4		T60	4
all_values[9]	auto[0]	auto[1]	auto[1]	29	1		T12	1		T14	2		T61	1
all_values[9]	auto[1]	auto[0]	auto[1]	62	1		T16	1		T12	1		T13	2
all_values[9]	auto[1]	auto[1]	auto[1]	44	1		T16	1		T12	1		T13	3
all_values[10]	auto[0]	auto[0]	auto[0]	71	1		T16	1		T13	2		T15	2
all_values[10]	auto[0]	auto[0]	auto[1]	18	1		T16	2		T60	1		T61	1
all_values[10]	auto[0]	auto[1]	auto[0]	54	1		T12	4		T13	2		T59	2
all_values[10]	auto[0]	auto[1]	auto[1]	17	1		T14	3		T61	2		T64	1
all_values[10]	auto[1]	auto[0]	auto[1]	52	1		T13	2		T14	1		T15	2
all_values[10]	auto[1]	auto[1]	auto[1]	42	1		T16	1		T13	1		T59	1
all_values[11]	auto[0]	auto[0]	auto[0]	55	1		T16	1		T13	1		T14	2
all_values[11]	auto[0]	auto[0]	auto[1]	30	1		T16	1		T12	1		T60	2
all_values[11]	auto[0]	auto[1]	auto[0]	43	1		T16	1		T12	1		T13	3
all_values[11]	auto[0]	auto[1]	auto[1]	20	1		T15	1		T63	1		T65	1
all_values[11]	auto[1]	auto[0]	auto[1]	53	1		T16	1		T12	1		T13	1
all_values[11]	auto[1]	auto[1]	auto[1]	53	1		T12	1		T13	2		T15	2
all_values[12]	auto[0]	auto[0]	auto[0]	50	1		T16	2		T13	4		T59	1
all_values[12]	auto[0]	auto[0]	auto[1]	29	1		T16	1		T12	2		T59	1
all_values[12]	auto[0]	auto[1]	auto[0]	52	1		T12	1		T13	3		T15	1
all_values[12]	auto[0]	auto[1]	auto[1]	21	1		T14	2		T15	1		T59	1
all_values[12]	auto[1]	auto[0]	auto[1]	63	1		T16	1		T14	1		T59	1
all_values[12]	auto[1]	auto[1]	auto[1]	39	1		T12	1		T14	1		T15	2
all_values[13]	auto[0]	auto[0]	auto[0]	46	1		T14	3		T62	1		T63	1
all_values[13]	auto[0]	auto[0]	auto[1]	31	1		T12	1		T13	1		T15	1
all_values[13]	auto[0]	auto[1]	auto[0]	48	1		T13	2		T59	2		T60	2
all_values[13]	auto[0]	auto[1]	auto[1]	24	1		T16	3		T15	1		T59	1
all_values[13]	auto[1]	auto[0]	auto[1]	69	1		T16	1		T12	3		T13	1
all_values[13]	auto[1]	auto[1]	auto[1]	36	1		T13	3		T15	1		T59	1
all_values[14]	auto[0]	auto[0]	auto[0]	52	1		T16	1		T12	1		T14	1
all_values[14]	auto[0]	auto[0]	auto[1]	23	1		T12	1		T13	1		T15	1
all_values[14]	auto[0]	auto[1]	auto[0]	52	1		T16	2		T14	1		T59	1
all_values[14]	auto[0]	auto[1]	auto[1]	23	1		T13	2		T14	1		T63	1
all_values[14]	auto[1]	auto[0]	auto[1]	56	1		T16	1		T12	2		T13	2
all_values[14]	auto[1]	auto[1]	auto[1]	48	1		T13	2		T14	1		T59	1
all_values[15]	auto[0]	auto[0]	auto[0]	58	1		T13	1		T14	3		T59	1
all_values[15]	auto[0]	auto[0]	auto[1]	31	1		T12	1		T13	1		T15	1
all_values[15]	auto[0]	auto[1]	auto[0]	48	1		T16	2		T13	1		T15	2
all_values[15]	auto[0]	auto[1]	auto[1]	10	1		T61	2		T64	1		T66	1
all_values[15]	auto[1]	auto[0]	auto[1]	64	1		T16	1		T12	1		T13	3
all_values[15]	auto[1]	auto[1]	auto[1]	43	1		T16	1		T12	2		T13	1
all_values[16]	auto[0]	auto[0]	auto[0]	47	1		T16	1		T60	2		T61	1
all_values[16]	auto[0]	auto[0]	auto[1]	29	1		T13	2		T59	1		T67	1
all_values[16]	auto[0]	auto[1]	auto[0]	41	1		T16	3		T12	4		T13	1
all_values[16]	auto[0]	auto[1]	auto[1]	23	1		T13	1		T15	1		T59	2
all_values[16]	auto[1]	auto[0]	auto[1]	58	1		T13	1		T14	1		T59	3
all_values[16]	auto[1]	auto[1]	auto[1]	56	1		T13	2		T14	2		T15	2
all_values[17]	auto[0]	auto[0]	auto[0]	78	1		T16	2		T12	1		T13	3
all_values[17]	auto[0]	auto[1]	auto[0]	70	1		T16	1		T13	2		T14	1
all_values[17]	auto[1]	auto[0]	auto[1]	47	1		T12	3		T59	3		T60	2
all_values[17]	auto[1]	auto[1]	auto[1]	59	1		T16	1		T13	2		T14	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal