Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9392982	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	9977303	1		T1	5		T2	17		T3	7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	18779894	1		T1	2		T2	13		T3	2
values[0x0]	294014	1		T1	4		T2	3		T3	7
values[0x1]	296377	1		T1	4		T2	5		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7465237	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	11905048	1		T1	7		T2	19		T3	7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	67112	1		T5	62		T6	56		T71	28
valid_sources[0x01]	78663	1		T30	1		T31	1		T5	61
valid_sources[0x02]	57711	1		T30	4		T5	66		T6	46
valid_sources[0x03]	155197	1		T30	1		T35	5		T5	61
valid_sources[0x04]	57850	1		T33	26		T5	54		T6	85
valid_sources[0x05]	58735	1		T31	1		T35	3		T5	57
valid_sources[0x06]	90952	1		T31	1		T5	56		T6	63
valid_sources[0x07]	57132	1		T5	69		T6	44		T71	21
valid_sources[0x08]	59101	1		T5	29		T6	70		T71	30
valid_sources[0x09]	62396	1		T5	34		T6	71		T71	29
valid_sources[0x0a]	58727	1		T1	3		T30	1		T5	68
valid_sources[0x0b]	68160	1		T5	57		T6	80		T71	39
valid_sources[0x0c]	58108	1		T5	54		T6	44		T71	20
valid_sources[0x0d]	149484	1		T35	6		T5	59		T6	53
valid_sources[0x0e]	77459	1		T5	53		T6	70		T71	29
valid_sources[0x0f]	128514	1		T5	50		T6	64		T71	34
valid_sources[0x10]	69279	1		T30	1		T5	47		T6	67
valid_sources[0x11]	179972	1		T5	65		T6	42		T71	26
valid_sources[0x12]	58076	1		T31	1		T35	4		T5	69
valid_sources[0x13]	68650	1		T30	3		T5	63		T6	91
valid_sources[0x14]	59251	1		T30	1		T31	1		T5	65
valid_sources[0x15]	58797	1		T5	74		T6	19		T71	38
valid_sources[0x16]	58776	1		T35	1		T5	54		T6	56
valid_sources[0x17]	57729	1		T30	1		T5	76		T6	73
valid_sources[0x18]	58390	1		T5	58		T6	53		T71	29
valid_sources[0x19]	76843	1		T35	10		T5	69		T6	60
valid_sources[0x1a]	71643	1		T30	1		T32	58		T5	81
valid_sources[0x1b]	57505	1		T5	60		T78	1		T6	60
valid_sources[0x1c]	57091	1		T5	50		T6	62		T71	29
valid_sources[0x1d]	73254	1		T5	52		T6	78		T71	36
valid_sources[0x1e]	57740	1		T30	1		T5	61		T6	79
valid_sources[0x1f]	65134	1		T5	70		T6	78		T71	23
valid_sources[0x20]	75489	1		T35	3		T5	40		T78	1
valid_sources[0x21]	56967	1		T35	2		T5	46		T6	87
valid_sources[0x22]	57346	1		T30	1		T35	4		T5	70
valid_sources[0x23]	59039	1		T5	56		T6	44		T71	23
valid_sources[0x24]	83656	1		T35	1		T5	76		T6	44
valid_sources[0x25]	59231	1		T34	1		T5	51		T6	56
valid_sources[0x26]	60541	1		T30	1		T5	76		T6	92
valid_sources[0x27]	81565	1		T30	2		T39	14		T5	60
valid_sources[0x28]	116607	1		T5	52		T6	50		T71	22
valid_sources[0x29]	58932	1		T5	35		T78	1		T6	84
valid_sources[0x2a]	59203	1		T5	62		T6	52		T71	29
valid_sources[0x2b]	68897	1		T5	67		T6	83		T71	37
valid_sources[0x2c]	77901	1		T35	5		T5	61		T6	51
valid_sources[0x2d]	87889	1		T30	1		T31	2		T35	1
valid_sources[0x2e]	58650	1		T5	80		T6	92		T71	16
valid_sources[0x2f]	106649	1		T30	1		T5	65		T6	81
valid_sources[0x30]	57775	1		T5	60		T6	68		T71	42
valid_sources[0x31]	59175	1		T30	1		T34	5		T5	61
valid_sources[0x32]	58252	1		T30	3		T34	1		T5	42
valid_sources[0x33]	101750	1		T30	1		T5	79		T6	50
valid_sources[0x34]	125341	1		T31	1		T5	78		T89	25
valid_sources[0x35]	77678	1		T5	47		T6	92		T71	45
valid_sources[0x36]	204610	1		T5	50		T6	61		T71	35
valid_sources[0x37]	58568	1		T30	1		T5	59		T6	54
valid_sources[0x38]	90570	1		T5	52		T6	51		T71	19
valid_sources[0x39]	57673	1		T5	46		T6	86		T71	39
valid_sources[0x3a]	57873	1		T30	3		T35	1		T5	65
valid_sources[0x3b]	57674	1		T5	66		T6	52		T71	44
valid_sources[0x3c]	70012	1		T35	1		T5	62		T6	78
valid_sources[0x3d]	62799	1		T31	1		T5	51		T6	60
valid_sources[0x3e]	128446	1		T35	3		T5	69		T6	46
valid_sources[0x3f]	58323	1		T5	88		T99	10		T6	80
valid_sources[0x40]	67746	1		T30	2		T5	66		T6	63
valid_sources[0x41]	77365	1		T5	94		T6	80		T71	24
valid_sources[0x42]	59314	1		T30	1		T35	8		T5	49
valid_sources[0x43]	74171	1		T30	1		T5	67		T6	71
valid_sources[0x44]	77946	1		T35	1		T5	64		T6	81
valid_sources[0x45]	92472	1		T3	1		T30	1		T5	85
valid_sources[0x46]	95461	1		T5	80		T6	93		T71	34
valid_sources[0x47]	116225	1		T5	91		T6	64		T71	32
valid_sources[0x48]	58630	1		T5	76		T6	56		T71	35
valid_sources[0x49]	73493	1		T30	1		T5	84		T6	78
valid_sources[0x4a]	58731	1		T5	66		T6	41		T71	37
valid_sources[0x4b]	58340	1		T5	49		T6	56		T71	30
valid_sources[0x4c]	58560	1		T3	4		T5	80		T78	1
valid_sources[0x4d]	96659	1		T30	1		T35	1		T5	74
valid_sources[0x4e]	58420	1		T30	1		T5	51		T6	57
valid_sources[0x4f]	58455	1		T5	92		T6	43		T71	37
valid_sources[0x50]	59496	1		T30	3		T5	50		T6	29
valid_sources[0x51]	58804	1		T5	94		T6	61		T71	25
valid_sources[0x52]	111594	1		T35	8		T5	59		T6	59
valid_sources[0x53]	78477	1		T35	1		T5	55		T6	79
valid_sources[0x54]	58218	1		T35	1		T5	68		T6	76
valid_sources[0x55]	193357	1		T30	5		T5	45		T6	46
valid_sources[0x56]	56867	1		T5	72		T6	49		T71	36
valid_sources[0x57]	59229	1		T35	3		T5	49		T6	80
valid_sources[0x58]	87587	1		T5	61		T6	71		T71	22
valid_sources[0x59]	57910	1		T5	45		T6	72		T71	45
valid_sources[0x5a]	56968	1		T1	2		T30	3		T5	68
valid_sources[0x5b]	57517	1		T5	56		T6	59		T71	33
valid_sources[0x5c]	95522	1		T5	45		T6	65		T71	34
valid_sources[0x5d]	58136	1		T30	1		T5	63		T6	111
valid_sources[0x5e]	64064	1		T5	37		T6	55		T71	32
valid_sources[0x5f]	70113	1		T30	1		T35	5		T5	80
valid_sources[0x60]	109613	1		T30	1		T5	60		T6	68
valid_sources[0x61]	58270	1		T5	58		T6	65		T71	24
valid_sources[0x62]	58298	1		T35	7		T5	51		T99	1
valid_sources[0x63]	57725	1		T34	4		T5	47		T6	42
valid_sources[0x64]	80596	1		T5	47		T6	64		T71	33
valid_sources[0x65]	58998	1		T30	2		T5	48		T6	61
valid_sources[0x66]	57538	1		T30	2		T5	72		T6	87
valid_sources[0x67]	57911	1		T30	1		T5	40		T6	136
valid_sources[0x68]	130341	1		T5	69		T6	46		T71	32
valid_sources[0x69]	59053	1		T30	1		T5	65		T6	84
valid_sources[0x6a]	58321	1		T3	3		T5	53		T6	65
valid_sources[0x6b]	59844	1		T5	72		T6	56		T71	38
valid_sources[0x6c]	59483	1		T5	54		T6	40		T71	34
valid_sources[0x6d]	84115	1		T5	65		T6	73		T71	16
valid_sources[0x6e]	58049	1		T5	30		T6	74		T71	25
valid_sources[0x6f]	57194	1		T5	70		T6	52		T71	23
valid_sources[0x70]	105693	1		T30	1		T35	3		T5	82
valid_sources[0x71]	68176	1		T35	2		T5	61		T6	41
valid_sources[0x72]	67179	1		T5	58		T6	86		T71	38
valid_sources[0x73]	59086	1		T5	77		T6	48		T71	29
valid_sources[0x74]	57472	1		T30	1		T5	73		T6	63
valid_sources[0x75]	57985	1		T1	1		T30	1		T5	48
valid_sources[0x76]	154698	1		T5	55		T6	46		T71	29
valid_sources[0x77]	78565	1		T5	80		T6	37		T71	28
valid_sources[0x78]	57155	1		T5	59		T6	34		T71	28
valid_sources[0x79]	58202	1		T30	1		T5	54		T6	55
valid_sources[0x7a]	58433	1		T31	2		T5	64		T6	89
valid_sources[0x7b]	59913	1		T35	6		T5	54		T6	92
valid_sources[0x7c]	58248	1		T31	1		T5	63		T6	35
valid_sources[0x7d]	167342	1		T35	1		T5	65		T6	58
valid_sources[0x7e]	67960	1		T5	50		T6	50		T71	17
valid_sources[0x7f]	124078	1		T31	2		T5	68		T6	67
valid_sources[0x80]	84570	1		T5	98		T6	49		T71	40

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9495135

1

T1

2

T2

12

T3

1

values[0x0]

all_enables

biggest_size

248008

1

T1

2

T2

3

T3

5

values[0x1]

all_enables

biggest_size

234160

1

T1

1

T2

2

T3

1