Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	9408656	1		T1	5		T2	4		T3	3
full_word	9978406	1		T1	5		T2	17		T3	7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	19386782	1		T1	10		T2	21		T3	10
auto[TlIntgErrCmd]	92	1		T230	1		T231	8		T232	2
auto[TlIntgErrData]	98	1		T230	6		T231	7		T232	2
auto[TlIntgErrBoth]	90	1		T230	3		T231	5		T232	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	18782032	1		T1	2		T2	13		T3	2
auto[1]	605030	1		T1	8		T2	8		T3	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9286608	1		T2	1		T3	1		T30	22
auto[TlIntgErrNone]	partial	auto[1]	121800	1		T1	5		T2	3		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	9495317	1		T1	2		T2	12		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	483057	1		T1	3		T2	5		T3	6
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T231	2		T238	3		T311	2
auto[TlIntgErrCmd]	partial	auto[1]	50	1		T230	1		T231	5		T232	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T314	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T231	1		T309	1		T315	1
auto[TlIntgErrData]	partial	auto[0]	35	1		T231	4		T232	2		T238	4
auto[TlIntgErrData]	partial	auto[1]	55	1		T230	5		T231	3		T238	4
auto[TlIntgErrData]	full_word	auto[0]	4	1		T311	1		T316	1		T317	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T230	1		T238	1		T318	2
auto[TlIntgErrBoth]	partial	auto[0]	24	1		T230	1		T232	1		T311	3
auto[TlIntgErrBoth]	partial	auto[1]	49	1		T230	2		T231	4		T232	5
auto[TlIntgErrBoth]	full_word	auto[0]	8	1		T231	1		T319	1		T309	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1		T238	1		T311	3		T313	1