Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	589181444	12109	0	0
ep_in_enable_rd_A	589181444	3312	0	0
ep_out_enable_rd_A	589181444	3752	0	0
in_iso_rd_A	589181444	3078	0	0
intr_enable_rd_A	589181444	5292	0	0
out_iso_rd_A	589181444	3296	0	0
phy_config_rd_A	589181444	2021	0	0
phy_pins_drive_rd_A	589181444	2852	0	0
rxenable_setup_rd_A	589181444	3543	0	0
set_nak_out_rd_A	589181444	3389	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589181444	12109	0	0
T203	3370	16	0	0
T204	3343	20	0	0
T205	2778	5	0	0
T221	5365	730	0	0
T222	8410	553	0	0
T223	9060	392	0	0
T228	7017	428	0	0
T230	38038	2	0	0
T233	10537	22	0	0
T243	5378	13	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589181444	3312	0	0
T230	38038	192	0	0
T231	35680	572	0	0
T233	10537	46	0	0
T254	4506	41	0	0
T255	2877	46	0	0
T269	5820	17	0	0
T272	3586	36	0	0
T273	13879	25	0	0
T278	5217	34	0	0
T279	9641	125	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589181444	3752	0	0
T230	38038	513	0	0
T231	35680	508	0	0
T233	10537	47	0	0
T254	4506	7	0	0
T255	2877	1	0	0
T269	5820	41	0	0
T272	3586	57	0	0
T273	13879	35	0	0
T278	5217	28	0	0
T279	9641	108	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589181444	3078	0	0
T223	9060	4	0	0
T230	38038	313	0	0
T231	35680	487	0	0
T233	10537	32	0	0
T254	4506	44	0	0
T255	2877	34	0	0
T269	5820	8	0	0
T273	13879	27	0	0
T278	5217	15	0	0
T279	9641	83	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589181444	5292	0	0
T213	1910	14	0	0
T214	2565	4	0	0
T230	38038	326	0	0
T233	10537	45	0	0
T269	5820	4	0	0
T272	3586	79	0	0
T273	13879	17	0	0
T280	1951	20	0	0
T281	2049	15	0	0
T282	1955	30	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589181444	3296	0	0
T230	38038	179	0	0
T231	35680	566	0	0
T233	10537	34	0	0
T254	4506	42	0	0
T255	2877	6	0	0
T269	5820	13	0	0
T272	3586	2	0	0
T273	13879	14	0	0
T279	9641	93	0	0
T283	6702	19	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589181444	2021	0	0
T230	38038	139	0	0
T231	35680	260	0	0
T233	10537	16	0	0
T254	4506	1	0	0
T255	2877	5	0	0
T269	5820	12	0	0
T272	3586	10	0	0
T273	13879	27	0	0
T278	5217	6	0	0
T279	9641	114	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589181444	2852	0	0
T230	38038	147	0	0
T231	35680	361	0	0
T233	10537	50	0	0
T254	4506	6	0	0
T269	5820	49	0	0
T272	3586	21	0	0
T273	13879	12	0	0
T278	5217	32	0	0
T279	9641	96	0	0
T283	6702	3	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589181444	3543	0	0
T230	38038	154	0	0
T231	35680	481	0	0
T233	10537	17	0	0
T254	4506	36	0	0
T255	2877	37	0	0
T269	5820	15	0	0
T272	3586	42	0	0
T273	13879	40	0	0
T278	5217	17	0	0
T279	9641	95	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589181444	3389	0	0
T230	38038	314	0	0
T231	35680	484	0	0
T233	10537	19	0	0
T254	4506	8	0	0
T255	2877	2	0	0
T269	5820	13	0	0
T272	3586	3	0	0
T273	13879	32	0	0
T278	5217	64	0	0
T279	9641	112	0	0