Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8877960	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	9493210	1		T1	3		T2	5629		T3	114

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	17768811	1		T1	3		T2	11086		T3	116
values[0x0]	300572	1		T1	3		T2	107		T3	6
values[0x1]	301787	1		T1	6		T2	120		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7060140	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	11311030	1		T1	5		T2	6753		T3	119

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53103	1		T4	32		T5	635		T7	5
valid_sources[0x01]	55830	1		T4	45		T5	535		T107	2
valid_sources[0x02]	136020	1		T4	47		T5	618		T107	5
valid_sources[0x03]	52472	1		T4	40		T5	585		T107	1
valid_sources[0x04]	106470	1		T4	32		T32	42		T34	1
valid_sources[0x05]	54075	1		T4	27		T5	638		T7	5
valid_sources[0x06]	55540	1		T4	29		T27	1		T5	630
valid_sources[0x07]	54486	1		T1	1		T4	22		T5	593
valid_sources[0x08]	55680	1		T4	34		T5	623		T7	6
valid_sources[0x09]	85910	1		T4	40		T33	1		T5	588
valid_sources[0x0a]	61432	1		T4	31		T5	543		T30	1
valid_sources[0x0b]	70536	1		T4	52		T5	612		T103	1
valid_sources[0x0c]	187993	1		T4	55		T5	607		T46	1
valid_sources[0x0d]	53040	1		T4	40		T5	572		T22	1
valid_sources[0x0e]	83456	1		T4	46		T5	640		T22	1
valid_sources[0x0f]	54407	1		T4	43		T5	551		T107	4
valid_sources[0x10]	53676	1		T4	37		T33	1		T5	657
valid_sources[0x11]	96730	1		T4	23		T5	558		T107	3
valid_sources[0x12]	64459	1		T4	37		T5	555		T30	2
valid_sources[0x13]	53704	1		T4	27		T5	669		T103	2
valid_sources[0x14]	70145	1		T4	48		T33	1		T5	595
valid_sources[0x15]	85523	1		T4	45		T5	546		T7	3
valid_sources[0x16]	53435	1		T4	52		T33	1		T5	605
valid_sources[0x17]	67618	1		T4	28		T5	553		T6	160
valid_sources[0x18]	54212	1		T4	33		T5	637		T107	4
valid_sources[0x19]	53228	1		T4	34		T33	2		T5	687
valid_sources[0x1a]	53232	1		T4	33		T34	1		T5	716
valid_sources[0x1b]	54721	1		T4	25		T5	786		T108	12
valid_sources[0x1c]	53692	1		T4	28		T5	643		T103	1
valid_sources[0x1d]	211162	1		T4	48		T33	1		T5	559
valid_sources[0x1e]	53825	1		T4	34		T33	1		T5	591
valid_sources[0x1f]	64622	1		T4	18		T5	777		T170	66
valid_sources[0x20]	97445	1		T4	39		T5	575		T46	4
valid_sources[0x21]	52456	1		T4	43		T5	629		T22	3
valid_sources[0x22]	68284	1		T4	40		T5	615		T107	3
valid_sources[0x23]	52698	1		T4	31		T5	607		T107	3
valid_sources[0x24]	57524	1		T4	38		T5	611		T61	1
valid_sources[0x25]	85559	1		T4	34		T5	625		T7	2
valid_sources[0x26]	54017	1		T4	28		T5	509		T22	1
valid_sources[0x27]	87387	1		T4	31		T33	1		T5	598
valid_sources[0x28]	53191	1		T4	54		T5	529		T107	2
valid_sources[0x29]	66907	1		T4	30		T5	618		T17	10
valid_sources[0x2a]	52906	1		T4	40		T5	614		T20	16
valid_sources[0x2b]	54656	1		T1	2		T4	59		T5	571
valid_sources[0x2c]	54801	1		T4	53		T5	541		T16	1
valid_sources[0x2d]	52567	1		T4	35		T5	661		T7	15
valid_sources[0x2e]	54509	1		T4	43		T5	667		T107	4
valid_sources[0x2f]	53312	1		T4	32		T5	556		T107	4
valid_sources[0x30]	53349	1		T4	30		T5	580		T7	5
valid_sources[0x31]	102942	1		T4	29		T34	1		T5	642
valid_sources[0x32]	53330	1		T4	17		T5	640		T103	1
valid_sources[0x33]	52153	1		T4	32		T5	645		T22	1
valid_sources[0x34]	53172	1		T4	44		T5	585		T22	1
valid_sources[0x35]	167288	1		T4	39		T5	635		T23	1
valid_sources[0x36]	53217	1		T4	43		T5	580		T107	4
valid_sources[0x37]	54142	1		T4	34		T5	613		T7	1
valid_sources[0x38]	228910	1		T4	48		T5	595		T18	1
valid_sources[0x39]	51801	1		T4	33		T33	1		T5	675
valid_sources[0x3a]	144661	1		T4	55		T33	1		T5	693
valid_sources[0x3b]	55365	1		T4	36		T5	624		T16	1
valid_sources[0x3c]	133900	1		T4	23		T5	595		T107	5
valid_sources[0x3d]	90328	1		T4	28		T34	1		T5	562
valid_sources[0x3e]	116338	1		T4	41		T5	534		T107	2
valid_sources[0x3f]	53416	1		T4	22		T5	544		T107	6
valid_sources[0x40]	54165	1		T4	37		T33	1		T5	470
valid_sources[0x41]	53346	1		T4	43		T5	522		T7	3
valid_sources[0x42]	52299	1		T4	28		T5	505		T18	7
valid_sources[0x43]	63369	1		T1	1		T2	11313		T4	38
valid_sources[0x44]	69232	1		T4	34		T5	618		T7	5
valid_sources[0x45]	71378	1		T4	30		T5	585		T22	1
valid_sources[0x46]	62289	1		T4	43		T5	605		T107	3
valid_sources[0x47]	55976	1		T4	40		T27	1		T5	644
valid_sources[0x48]	74676	1		T4	51		T5	619		T107	4
valid_sources[0x49]	55282	1		T4	44		T33	1		T34	1
valid_sources[0x4a]	51944	1		T4	44		T5	545		T107	3
valid_sources[0x4b]	54259	1		T4	50		T5	597		T22	1
valid_sources[0x4c]	142040	1		T4	36		T5	568		T46	1
valid_sources[0x4d]	53672	1		T4	63		T5	663		T107	7
valid_sources[0x4e]	69351	1		T4	47		T33	1		T5	527
valid_sources[0x4f]	53037	1		T4	51		T5	692		T22	2
valid_sources[0x50]	52852	1		T4	43		T5	602		T40	1
valid_sources[0x51]	52694	1		T4	29		T5	628		T131	1
valid_sources[0x52]	56115	1		T4	20		T5	631		T61	1
valid_sources[0x53]	79552	1		T4	26		T5	608		T107	4
valid_sources[0x54]	54352	1		T4	32		T5	587		T16	1
valid_sources[0x55]	54468	1		T4	47		T27	1		T33	1
valid_sources[0x56]	52448	1		T4	29		T5	579		T103	1
valid_sources[0x57]	169055	1		T4	25		T5	641		T7	3
valid_sources[0x58]	52761	1		T4	29		T5	534		T18	2
valid_sources[0x59]	70124	1		T4	55		T5	572		T103	3
valid_sources[0x5a]	66285	1		T1	1		T4	27		T33	1
valid_sources[0x5b]	149077	1		T4	27		T5	572		T107	7
valid_sources[0x5c]	53938	1		T4	28		T27	1		T5	623
valid_sources[0x5d]	52807	1		T4	40		T5	536		T22	2
valid_sources[0x5e]	53139	1		T4	43		T5	595		T107	8
valid_sources[0x5f]	52165	1		T4	36		T5	487		T23	1
valid_sources[0x60]	52567	1		T4	32		T5	631		T103	1
valid_sources[0x61]	56084	1		T4	45		T5	626		T468	1
valid_sources[0x62]	108477	1		T4	34		T34	1		T5	530
valid_sources[0x63]	53952	1		T4	30		T5	619		T23	1
valid_sources[0x64]	53027	1		T4	35		T33	1		T5	676
valid_sources[0x65]	217577	1		T4	45		T34	2		T5	622
valid_sources[0x66]	53500	1		T4	62		T33	1		T5	625
valid_sources[0x67]	64347	1		T4	39		T5	620		T7	16
valid_sources[0x68]	54122	1		T4	44		T5	541		T23	1
valid_sources[0x69]	54009	1		T4	48		T5	513		T103	1
valid_sources[0x6a]	56578	1		T4	35		T5	563		T22	1
valid_sources[0x6b]	105625	1		T4	39		T27	1		T5	679
valid_sources[0x6c]	55641	1		T4	34		T5	707		T22	1
valid_sources[0x6d]	69860	1		T4	47		T33	1		T5	581
valid_sources[0x6e]	81138	1		T1	1		T4	44		T5	568
valid_sources[0x6f]	82502	1		T4	40		T33	1		T5	517
valid_sources[0x70]	64737	1		T4	29		T5	629		T107	5
valid_sources[0x71]	53282	1		T4	35		T5	567		T107	4
valid_sources[0x72]	52143	1		T4	30		T5	661		T107	9
valid_sources[0x73]	85274	1		T4	54		T5	576		T16	1
valid_sources[0x74]	87762	1		T4	42		T33	1		T5	591
valid_sources[0x75]	61339	1		T4	47		T5	584		T16	1
valid_sources[0x76]	54159	1		T4	27		T5	598		T107	3
valid_sources[0x77]	54006	1		T4	26		T27	1		T5	627
valid_sources[0x78]	54132	1		T4	35		T5	629		T107	8
valid_sources[0x79]	69961	1		T1	1		T4	43		T5	592
valid_sources[0x7a]	86437	1		T4	42		T33	1		T5	600
valid_sources[0x7b]	132438	1		T4	39		T5	608		T107	6
valid_sources[0x7c]	54009	1		T4	18		T5	610		T103	1
valid_sources[0x7d]	69970	1		T4	60		T5	587		T22	2
valid_sources[0x7e]	68146	1		T4	30		T5	633		T7	3
valid_sources[0x7f]	52319	1		T4	30		T33	2		T5	573
valid_sources[0x80]	104139	1		T4	35		T5	526		T107	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9001983

1

T2

5469

T3

109

T4

4703

values[0x0]

all_enables

biggest_size

253187

1

T1

1

T2

75

T3

2

values[0x1]

all_enables

biggest_size

238040

1

T1

2

T2

85

T3

3