Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	8892097	1		T1	9		T2	5684		T3	15
full_word	9494178	1		T1	3		T2	5629		T3	114

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	18385975	1		T1	12		T2	11313		T3	129
auto[TlIntgErrCmd]	114	1		T225	6		T226	8		T251	5
auto[TlIntgErrData]	94	1		T226	5		T251	4		T269	4
auto[TlIntgErrBoth]	92	1		T225	4		T226	7		T251	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	17770638	1		T1	3		T2	11086		T3	116
auto[1]	615637	1		T1	9		T2	227		T3	13

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8768357	1		T1	3		T2	5617		T3	7
auto[TlIntgErrNone]	partial	auto[1]	123461	1		T1	6		T2	67		T3	8
auto[TlIntgErrNone]	full_word	auto[0]	9002150	1		T2	5469		T3	109		T4	4703
auto[TlIntgErrNone]	full_word	auto[1]	492007	1		T1	3		T2	160		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	41	1		T226	3		T251	2		T269	2
auto[TlIntgErrCmd]	partial	auto[1]	62	1		T225	5		T226	4		T251	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T474	2		T476	1		T477	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T225	1		T226	1		T251	1
auto[TlIntgErrData]	partial	auto[0]	45	1		T226	4		T251	4		T269	3
auto[TlIntgErrData]	partial	auto[1]	45	1		T226	1		T269	1		T474	1
auto[TlIntgErrData]	full_word	auto[0]	2	1		T478	1		T479	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1		T475	1		T478	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	34	1		T225	3		T226	2		T251	7
auto[TlIntgErrBoth]	partial	auto[1]	52	1		T225	1		T226	4		T251	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T226	1		T251	1		T268	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T475	1		-	-		-	-