Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	585641844	11164	0	0
ep_in_enable_rd_A	585641844	3934	0	0
ep_out_enable_rd_A	585641844	3896	0	0
in_iso_rd_A	585641844	3681	0	0
intr_enable_rd_A	585641844	5211	0	0
out_iso_rd_A	585641844	3761	0	0
phy_config_rd_A	585641844	2608	0	0
phy_pins_drive_rd_A	585641844	3027	0	0
rxenable_setup_rd_A	585641844	4005	0	0
set_nak_out_rd_A	585641844	3398	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585641844	11164	0	0
T224	8431	13	0	0
T225	24713	2	0	0
T226	32764	3	0	0
T249	5999	9	0	0
T250	3829	17	0	0
T251	40494	3	0	0
T255	5659	984	0	0
T256	6908	440	0	0
T258	7089	19	0	0
T269	28832	3	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585641844	3934	0	0
T224	8431	7	0	0
T228	51376	171	0	0
T251	40494	269	0	0
T292	75200	293	0	0
T301	3921	12	0	0
T309	4353	65	0	0
T310	2759	1	0	0
T311	9504	96	0	0
T312	7885	18	0	0
T313	43034	383	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585641844	3896	0	0
T224	8431	22	0	0
T228	51376	110	0	0
T251	40494	241	0	0
T292	75200	255	0	0
T301	3921	37	0	0
T304	7507	19	0	0
T309	4353	44	0	0
T311	9504	38	0	0
T312	7885	72	0	0
T313	43034	367	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585641844	3681	0	0
T224	8431	57	0	0
T228	51376	171	0	0
T251	40494	334	0	0
T292	75200	311	0	0
T301	3921	7	0	0
T304	7507	24	0	0
T309	4353	61	0	0
T310	2759	5	0	0
T311	9504	64	0	0
T312	7885	91	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585641844	5211	0	0
T224	8431	34	0	0
T228	51376	119	0	0
T251	40494	499	0	0
T301	3921	155	0	0
T304	7507	24	0	0
T309	4353	78	0	0
T314	4937	7	0	0
T315	3128	12	0	0
T316	2114	15	0	0
T317	2246	8	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585641844	3761	0	0
T224	8431	46	0	0
T228	51376	105	0	0
T251	40494	405	0	0
T292	75200	280	0	0
T301	3921	54	0	0
T304	7507	8	0	0
T309	4353	44	0	0
T310	2759	48	0	0
T311	9504	88	0	0
T312	7885	22	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585641844	2608	0	0
T224	8431	25	0	0
T228	51376	127	0	0
T251	40494	102	0	0
T292	75200	236	0	0
T301	3921	7	0	0
T304	7507	17	0	0
T309	4353	20	0	0
T310	2759	32	0	0
T311	9504	49	0	0
T312	7885	30	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585641844	3027	0	0
T224	8431	34	0	0
T228	51376	126	0	0
T251	40494	219	0	0
T292	75200	291	0	0
T301	3921	48	0	0
T304	7507	3	0	0
T309	4353	1	0	0
T310	2759	3	0	0
T311	9504	39	0	0
T312	7885	54	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585641844	4005	0	0
T224	8431	6	0	0
T228	51376	111	0	0
T251	40494	310	0	0
T292	75200	220	0	0
T301	3921	99	0	0
T309	4353	43	0	0
T310	2759	45	0	0
T311	9504	50	0	0
T312	7885	66	0	0
T313	43034	178	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585641844	3398	0	0
T224	8431	12	0	0
T228	51376	139	0	0
T251	40494	225	0	0
T292	75200	270	0	0
T301	3921	14	0	0
T304	7507	20	0	0
T309	4353	4	0	0
T311	9504	11	0	0
T312	7885	4	0	0
T313	43034	162	0	0