Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9471954	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	9994718	1		T1	146		T2	7		T3	6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	18902027	1		T1	152		T2	3		T3	4
values[0x0]	282407	1		T1	39		T2	6		T3	4
values[0x1]	282238	1		T1	38		T2	3		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7528789	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	11937883	1		T1	170		T2	8		T3	9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	60446	1		T7	3		T4	126		T6	304
valid_sources[0x01]	58164	1		T7	3		T4	111		T6	270
valid_sources[0x02]	57050	1		T4	181		T6	241		T30	22
valid_sources[0x03]	57670	1		T7	2		T4	233		T6	265
valid_sources[0x04]	56465	1		T7	2		T4	161		T6	300
valid_sources[0x05]	57149	1		T7	1		T4	181		T6	269
valid_sources[0x06]	151285	1		T4	173		T6	274		T30	38
valid_sources[0x07]	127614	1		T4	192		T6	255		T30	16
valid_sources[0x08]	59785	1		T4	181		T6	267		T30	16
valid_sources[0x09]	70455	1		T7	1		T4	123		T6	301
valid_sources[0x0a]	91083	1		T7	2		T4	149		T6	265
valid_sources[0x0b]	142125	1		T7	1		T4	175		T6	281
valid_sources[0x0c]	58657	1		T7	1		T4	131		T6	273
valid_sources[0x0d]	57546	1		T7	1		T4	106		T6	289
valid_sources[0x0e]	100762	1		T7	3		T4	147		T6	269
valid_sources[0x0f]	57094	1		T7	2		T4	162		T6	282
valid_sources[0x10]	58071	1		T7	3		T4	195		T6	287
valid_sources[0x11]	75623	1		T7	2		T4	209		T6	323
valid_sources[0x12]	58613	1		T7	5		T4	187		T6	276
valid_sources[0x13]	58836	1		T7	2		T4	238		T6	236
valid_sources[0x14]	57814	1		T7	2		T4	99		T6	252
valid_sources[0x15]	57459	1		T7	2		T4	155		T6	265
valid_sources[0x16]	63111	1		T3	1		T7	2		T4	141
valid_sources[0x17]	57672	1		T27	2		T7	2		T4	162
valid_sources[0x18]	76133	1		T7	1		T4	160		T6	239
valid_sources[0x19]	58114	1		T7	1		T4	118		T6	269
valid_sources[0x1a]	73568	1		T4	193		T6	278		T30	16
valid_sources[0x1b]	156572	1		T7	1		T4	151		T6	278
valid_sources[0x1c]	57325	1		T7	2		T4	179		T6	271
valid_sources[0x1d]	145318	1		T7	3		T4	218		T6	313
valid_sources[0x1e]	57698	1		T7	2		T4	144		T6	245
valid_sources[0x1f]	58046	1		T7	2		T4	174		T22	3
valid_sources[0x20]	58496	1		T17	1		T4	143		T6	245
valid_sources[0x21]	57570	1		T7	3		T4	208		T6	267
valid_sources[0x22]	56931	1		T4	98		T6	237		T30	22
valid_sources[0x23]	57019	1		T7	2		T4	159		T6	294
valid_sources[0x24]	87672	1		T4	149		T6	276		T30	11
valid_sources[0x25]	119341	1		T17	1		T4	136		T6	255
valid_sources[0x26]	66193	1		T7	2		T4	179		T6	266
valid_sources[0x27]	58683	1		T7	1		T4	186		T6	258
valid_sources[0x28]	56681	1		T7	1		T4	193		T6	275
valid_sources[0x29]	56829	1		T4	132		T6	272		T30	15
valid_sources[0x2a]	57814	1		T7	4		T4	130		T6	271
valid_sources[0x2b]	58100	1		T4	142		T6	304		T30	15
valid_sources[0x2c]	57508	1		T7	2		T17	1		T4	171
valid_sources[0x2d]	132103	1		T7	1		T4	135		T6	269
valid_sources[0x2e]	145480	1		T7	5		T4	145		T6	289
valid_sources[0x2f]	57277	1		T7	2		T4	144		T6	295
valid_sources[0x30]	67460	1		T4	165		T6	249		T30	13
valid_sources[0x31]	58257	1		T7	3		T4	158		T6	252
valid_sources[0x32]	59261	1		T3	3		T7	3		T4	176
valid_sources[0x33]	57891	1		T7	3		T4	165		T6	264
valid_sources[0x34]	77077	1		T4	160		T6	290		T30	18
valid_sources[0x35]	57335	1		T7	2		T4	130		T6	253
valid_sources[0x36]	57028	1		T7	1		T4	254		T6	265
valid_sources[0x37]	65545	1		T7	1		T4	131		T6	295
valid_sources[0x38]	57373	1		T3	1		T27	1		T7	1
valid_sources[0x39]	63467	1		T7	2		T4	137		T6	262
valid_sources[0x3a]	59480	1		T2	3		T4	171		T6	268
valid_sources[0x3b]	57639	1		T7	1		T4	144		T6	277
valid_sources[0x3c]	65737	1		T7	1		T4	123		T6	319
valid_sources[0x3d]	57832	1		T7	1		T4	131		T6	271
valid_sources[0x3e]	75510	1		T7	1		T4	164		T6	246
valid_sources[0x3f]	57514	1		T7	2		T4	160		T6	290
valid_sources[0x40]	118587	1		T7	1		T4	149		T6	253
valid_sources[0x41]	58360	1		T4	128		T6	308		T30	5
valid_sources[0x42]	57944	1		T7	4		T4	156		T6	279
valid_sources[0x43]	70225	1		T4	159		T6	296		T30	29
valid_sources[0x44]	57427	1		T7	2		T4	158		T6	255
valid_sources[0x45]	107980	1		T7	1		T17	1		T4	146
valid_sources[0x46]	56873	1		T27	1		T7	3		T4	204
valid_sources[0x47]	57705	1		T2	1		T7	1		T4	185
valid_sources[0x48]	57153	1		T7	2		T4	174		T21	8
valid_sources[0x49]	67532	1		T7	2		T17	1		T4	159
valid_sources[0x4a]	72472	1		T7	1		T4	122		T6	257
valid_sources[0x4b]	74871	1		T7	3		T4	100		T6	265
valid_sources[0x4c]	81670	1		T7	2		T4	125		T6	271
valid_sources[0x4d]	57724	1		T7	1		T4	185		T6	283
valid_sources[0x4e]	58149	1		T7	2		T4	142		T6	277
valid_sources[0x4f]	57872	1		T7	5		T4	116		T6	267
valid_sources[0x50]	57427	1		T7	1		T4	195		T6	253
valid_sources[0x51]	67262	1		T4	115		T22	4		T6	273
valid_sources[0x52]	175646	1		T1	229		T2	1		T3	2
valid_sources[0x53]	59097	1		T2	5		T4	164		T6	272
valid_sources[0x54]	92038	1		T7	3		T4	137		T6	283
valid_sources[0x55]	68721	1		T7	1		T4	188		T6	236
valid_sources[0x56]	59660	1		T27	1		T7	5		T4	169
valid_sources[0x57]	57574	1		T7	1		T4	158		T6	245
valid_sources[0x58]	134842	1		T7	1		T4	174		T6	260
valid_sources[0x59]	58395	1		T7	2		T4	209		T6	272
valid_sources[0x5a]	57777	1		T7	1		T4	155		T6	289
valid_sources[0x5b]	58716	1		T4	165		T6	248		T29	1
valid_sources[0x5c]	56650	1		T27	2		T7	4		T4	154
valid_sources[0x5d]	57564	1		T7	7		T4	185		T6	242
valid_sources[0x5e]	58038	1		T7	1		T4	128		T6	298
valid_sources[0x5f]	68280	1		T7	7		T4	129		T6	264
valid_sources[0x60]	57414	1		T4	150		T6	293		T30	22
valid_sources[0x61]	57755	1		T27	1		T7	1		T4	150
valid_sources[0x62]	83110	1		T7	3		T4	173		T6	266
valid_sources[0x63]	59007	1		T4	113		T6	275		T30	21
valid_sources[0x64]	84565	1		T7	3		T4	193		T6	266
valid_sources[0x65]	162462	1		T7	2		T4	176		T6	293
valid_sources[0x66]	73793	1		T7	2		T4	137		T6	311
valid_sources[0x67]	102126	1		T7	1		T4	167		T6	308
valid_sources[0x68]	59577	1		T4	216		T6	262		T30	17
valid_sources[0x69]	57235	1		T7	2		T4	160		T6	276
valid_sources[0x6a]	96325	1		T7	1		T4	189		T6	252
valid_sources[0x6b]	58125	1		T7	4		T4	128		T6	284
valid_sources[0x6c]	58396	1		T7	2		T4	136		T6	257
valid_sources[0x6d]	56109	1		T7	1		T4	188		T6	266
valid_sources[0x6e]	65931	1		T7	1		T4	145		T6	283
valid_sources[0x6f]	180713	1		T7	1		T4	219		T22	1
valid_sources[0x70]	56918	1		T7	1		T4	229		T6	235
valid_sources[0x71]	57658	1		T4	129		T6	239		T29	3
valid_sources[0x72]	57189	1		T4	146		T6	289		T30	20
valid_sources[0x73]	126353	1		T4	160		T6	269		T30	14
valid_sources[0x74]	56714	1		T7	3		T4	146		T6	298
valid_sources[0x75]	57465	1		T7	1		T4	115		T6	290
valid_sources[0x76]	55995	1		T7	2		T17	1		T4	139
valid_sources[0x77]	149782	1		T7	1		T4	171		T6	251
valid_sources[0x78]	56929	1		T7	1		T4	148		T6	280
valid_sources[0x79]	70105	1		T7	1		T4	172		T22	1
valid_sources[0x7a]	57020	1		T7	4		T4	158		T6	256
valid_sources[0x7b]	110571	1		T7	2		T4	155		T6	268
valid_sources[0x7c]	58285	1		T7	3		T4	119		T6	263
valid_sources[0x7d]	157963	1		T4	179		T6	272		T30	13
valid_sources[0x7e]	75684	1		T3	1		T7	1		T4	129
valid_sources[0x7f]	57078	1		T7	2		T4	185		T6	298
valid_sources[0x80]	57855	1		T17	1		T4	128		T6	260

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9539296

1

T1

108

T2

1

T3

2

values[0x0]

all_enables

biggest_size

235720

1

T1

25

T2

5

T3

3

values[0x1]

all_enables

biggest_size

219702

1

T1

13

T2

1

T3

1