Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	9487010	1		T1	83		T2	5		T3	7
full_word	9995704	1		T1	146		T2	7		T3	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	19482444	1		T1	229		T2	12		T3	13
auto[TlIntgErrCmd]	83	1		T241	5		T246	6		T247	4
auto[TlIntgErrData]	98	1		T241	3		T246	11		T247	2
auto[TlIntgErrBoth]	89	1		T241	2		T246	3		T247	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	18903926	1		T1	152		T2	3		T3	4
auto[1]	578788	1		T1	77		T2	9		T3	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrData]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9364365	1		T1	44		T2	2		T3	2
auto[TlIntgErrNone]	partial	auto[1]	122387	1		T1	39		T2	3		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	9539455	1		T1	108		T2	1		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	456237	1		T1	38		T2	6		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	29	1		T241	1		T246	1		T247	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1		T241	4		T246	3		T247	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T246	1		T335	1		T336	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T246	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	42	1		T241	1		T246	1		T247	1
auto[TlIntgErrData]	partial	auto[1]	52	1		T241	1		T246	10		T337	4
auto[TlIntgErrData]	full_word	auto[1]	4	1		T241	1		T247	1		T338	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T246	1		T247	3		T337	1
auto[TlIntgErrBoth]	partial	auto[1]	55	1		T241	2		T246	2		T247	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T337	1		T339	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T340	1		T336	1		-	-