Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	579503284	13093	0	0
ep_in_enable_rd_A	579503284	2608	0	0
ep_out_enable_rd_A	579503284	2284	0	0
in_iso_rd_A	579503284	2319	0	0
intr_enable_rd_A	579503284	3338	0	0
out_iso_rd_A	579503284	2195	0	0
phy_config_rd_A	579503284	1771	0	0
phy_pins_drive_rd_A	579503284	2082	0	0
rxenable_setup_rd_A	579503284	2372	0	0
set_nak_out_rd_A	579503284	2316	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579503284	13093	0	0
T215	3711	16	0	0
T216	4806	8	0	0
T217	4683	23	0	0
T241	14567	2	0	0
T242	7764	381	0	0
T244	9894	396	0	0
T245	4334	20	0	0
T257	6703	21	0	0
T261	3857	24	0	0
T262	3879	8	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579503284	2608	0	0
T216	4806	3	0	0
T218	21589	20	0	0
T272	2702	8	0	0
T274	3162	40	0	0
T277	7124	8	0	0
T301	14977	94	0	0
T302	7947	98	0	0
T303	8207	7	0	0
T304	19328	305	0	0
T305	8693	49	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579503284	2284	0	0
T216	4806	22	0	0
T218	21589	19	0	0
T244	9894	4	0	0
T272	2702	43	0	0
T274	3162	4	0	0
T301	14977	93	0	0
T302	7947	87	0	0
T303	8207	77	0	0
T304	19328	70	0	0
T305	8693	13	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579503284	2319	0	0
T216	4806	8	0	0
T218	21589	35	0	0
T272	2702	5	0	0
T274	3162	38	0	0
T279	6246	8	0	0
T301	14977	88	0	0
T302	7947	42	0	0
T303	8207	9	0	0
T304	19328	260	0	0
T305	8693	58	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579503284	3338	0	0
T216	4806	39	0	0
T218	21589	41	0	0
T272	2702	50	0	0
T301	14977	98	0	0
T302	7947	146	0	0
T303	8207	52	0	0
T306	2139	17	0	0
T307	3049	16	0	0
T308	3056	1	0	0
T309	2168	14	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579503284	2195	0	0
T218	21589	11	0	0
T272	2702	52	0	0
T274	3162	2	0	0
T277	7124	4	0	0
T279	6246	52	0	0
T301	14977	114	0	0
T302	7947	77	0	0
T303	8207	5	0	0
T304	19328	221	0	0
T305	8693	16	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579503284	1771	0	0
T218	21589	38	0	0
T272	2702	3	0	0
T274	3162	3	0	0
T279	6246	21	0	0
T281	74562	410	0	0
T301	14977	102	0	0
T302	7947	70	0	0
T303	8207	15	0	0
T304	19328	180	0	0
T305	8693	25	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579503284	2082	0	0
T216	4806	3	0	0
T218	21589	30	0	0
T272	2702	6	0	0
T274	3162	38	0	0
T279	6246	29	0	0
T301	14977	93	0	0
T302	7947	16	0	0
T303	8207	10	0	0
T304	19328	211	0	0
T305	8693	62	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579503284	2372	0	0
T216	4806	35	0	0
T218	21589	4	0	0
T274	3162	2	0	0
T277	7124	1	0	0
T279	6246	47	0	0
T301	14977	78	0	0
T302	7947	44	0	0
T303	8207	2	0	0
T304	19328	284	0	0
T305	8693	53	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579503284	2316	0	0
T216	4806	17	0	0
T218	21589	44	0	0
T272	2702	47	0	0
T274	3162	4	0	0
T277	7124	9	0	0
T301	14977	80	0	0
T302	7947	52	0	0
T303	8207	46	0	0
T304	19328	71	0	0
T305	8693	18	0	0