Line Coverage for Instance : tb.dut.usbdev_avsetupfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
140 |
1 |
1 |
Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo
| Total | Covered | Percent |
Conditions | 14 | 10 | 71.43 |
Logical | 14 | 10 | 71.43 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T20,T21 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T4,T20 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T21,T58 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T4,T20 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T3,T4,T20 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T4,T6 |
Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T20 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
144770939 |
0 |
0 |
T3 |
7235 |
596 |
0 |
0 |
T4 |
88775 |
81791 |
0 |
0 |
T5 |
514510 |
0 |
0 |
0 |
T6 |
0 |
139273 |
0 |
0 |
T7 |
696192 |
0 |
0 |
0 |
T17 |
7330 |
0 |
0 |
0 |
T18 |
9005 |
0 |
0 |
0 |
T19 |
1469 |
0 |
0 |
0 |
T20 |
8577 |
2076 |
0 |
0 |
T21 |
7547 |
1040 |
0 |
0 |
T27 |
11314 |
0 |
0 |
0 |
T29 |
0 |
11836 |
0 |
0 |
T31 |
0 |
563 |
0 |
0 |
T81 |
0 |
18680 |
0 |
0 |
T92 |
0 |
136168 |
0 |
0 |
T102 |
0 |
5825 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
577378822 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
577378822 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
577378822 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
144770939 |
0 |
0 |
T3 |
7235 |
596 |
0 |
0 |
T4 |
88775 |
81791 |
0 |
0 |
T5 |
514510 |
0 |
0 |
0 |
T6 |
0 |
139273 |
0 |
0 |
T7 |
696192 |
0 |
0 |
0 |
T17 |
7330 |
0 |
0 |
0 |
T18 |
9005 |
0 |
0 |
0 |
T19 |
1469 |
0 |
0 |
0 |
T20 |
8577 |
2076 |
0 |
0 |
T21 |
7547 |
1040 |
0 |
0 |
T27 |
11314 |
0 |
0 |
0 |
T29 |
0 |
11836 |
0 |
0 |
T31 |
0 |
563 |
0 |
0 |
T81 |
0 |
18680 |
0 |
0 |
T92 |
0 |
136168 |
0 |
0 |
T102 |
0 |
5825 |
0 |
0 |
Line Coverage for Instance : tb.dut.usbdev_avoutfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
140 |
1 |
1 |
Cond Coverage for Instance : tb.dut.usbdev_avoutfifo
| Total | Covered | Percent |
Conditions | 14 | 10 | 71.43 |
Logical | 14 | 10 | 71.43 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T20,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T27 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T59,T103,T104 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T27 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T27 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T27 |
Branch Coverage for Instance : tb.dut.usbdev_avoutfifo
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T27 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.usbdev_avoutfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
290937758 |
0 |
0 |
T1 |
44874 |
16231 |
0 |
0 |
T2 |
12041 |
2374 |
0 |
0 |
T3 |
7235 |
0 |
0 |
0 |
T4 |
88775 |
81775 |
0 |
0 |
T6 |
0 |
139257 |
0 |
0 |
T7 |
696192 |
0 |
0 |
0 |
T17 |
7330 |
302 |
0 |
0 |
T18 |
9005 |
2938 |
0 |
0 |
T19 |
1469 |
0 |
0 |
0 |
T20 |
8577 |
2142 |
0 |
0 |
T22 |
0 |
646 |
0 |
0 |
T27 |
11314 |
1712 |
0 |
0 |
T28 |
0 |
407484 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
577378822 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
577378822 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
577378822 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
290937758 |
0 |
0 |
T1 |
44874 |
16231 |
0 |
0 |
T2 |
12041 |
2374 |
0 |
0 |
T3 |
7235 |
0 |
0 |
0 |
T4 |
88775 |
81775 |
0 |
0 |
T6 |
0 |
139257 |
0 |
0 |
T7 |
696192 |
0 |
0 |
0 |
T17 |
7330 |
302 |
0 |
0 |
T18 |
9005 |
2938 |
0 |
0 |
T19 |
1469 |
0 |
0 |
0 |
T20 |
8577 |
2142 |
0 |
0 |
T22 |
0 |
646 |
0 |
0 |
T27 |
11314 |
1712 |
0 |
0 |
T28 |
0 |
407484 |
0 |
0 |
Line Coverage for Instance : tb.dut.usbdev_rxfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.usbdev_rxfifo
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T29,T44,T45 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T27,T17 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.usbdev_rxfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.usbdev_rxfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
50557628 |
0 |
0 |
T1 |
44874 |
1138 |
0 |
0 |
T2 |
12041 |
3209 |
0 |
0 |
T3 |
7235 |
935 |
0 |
0 |
T4 |
88775 |
265 |
0 |
0 |
T6 |
0 |
389 |
0 |
0 |
T7 |
696192 |
0 |
0 |
0 |
T17 |
7330 |
97 |
0 |
0 |
T18 |
9005 |
0 |
0 |
0 |
T19 |
1469 |
0 |
0 |
0 |
T20 |
8577 |
0 |
0 |
0 |
T22 |
0 |
93 |
0 |
0 |
T27 |
11314 |
112 |
0 |
0 |
T28 |
0 |
96434 |
0 |
0 |
T29 |
0 |
10997 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
577378822 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
577378822 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
577378822 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
50557628 |
0 |
0 |
T1 |
44874 |
1138 |
0 |
0 |
T2 |
12041 |
3209 |
0 |
0 |
T3 |
7235 |
935 |
0 |
0 |
T4 |
88775 |
265 |
0 |
0 |
T6 |
0 |
389 |
0 |
0 |
T7 |
696192 |
0 |
0 |
0 |
T17 |
7330 |
97 |
0 |
0 |
T18 |
9005 |
0 |
0 |
0 |
T19 |
1469 |
0 |
0 |
0 |
T20 |
8577 |
0 |
0 |
0 |
T22 |
0 |
93 |
0 |
0 |
T27 |
11314 |
112 |
0 |
0 |
T28 |
0 |
96434 |
0 |
0 |
T29 |
0 |
10997 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
19808525 |
0 |
0 |
T1 |
44874 |
229 |
0 |
0 |
T2 |
12041 |
12 |
0 |
0 |
T3 |
7235 |
13 |
0 |
0 |
T4 |
88775 |
40513 |
0 |
0 |
T7 |
696192 |
393 |
0 |
0 |
T17 |
7330 |
12 |
0 |
0 |
T18 |
9005 |
10 |
0 |
0 |
T19 |
1469 |
7 |
0 |
0 |
T20 |
8577 |
717 |
0 |
0 |
T27 |
11314 |
15 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
579230705 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
579230705 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
579230705 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3232 |
3232 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
28087962 |
0 |
0 |
T1 |
44874 |
229 |
0 |
0 |
T2 |
12041 |
12 |
0 |
0 |
T3 |
7235 |
13 |
0 |
0 |
T4 |
88775 |
40513 |
0 |
0 |
T7 |
696192 |
393 |
0 |
0 |
T17 |
7330 |
26 |
0 |
0 |
T18 |
9005 |
38 |
0 |
0 |
T19 |
1469 |
7 |
0 |
0 |
T20 |
8577 |
717 |
0 |
0 |
T27 |
11314 |
15 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
579230705 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
579230705 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
579230705 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3232 |
3232 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
879617 |
0 |
0 |
T1 |
44874 |
102 |
0 |
0 |
T2 |
12041 |
0 |
0 |
0 |
T3 |
7235 |
0 |
0 |
0 |
T4 |
88775 |
0 |
0 |
0 |
T5 |
0 |
2865 |
0 |
0 |
T6 |
0 |
28 |
0 |
0 |
T7 |
696192 |
0 |
0 |
0 |
T17 |
7330 |
0 |
0 |
0 |
T18 |
9005 |
0 |
0 |
0 |
T19 |
1469 |
0 |
0 |
0 |
T20 |
8577 |
0 |
0 |
0 |
T22 |
0 |
3 |
0 |
0 |
T27 |
11314 |
0 |
0 |
0 |
T28 |
0 |
12800 |
0 |
0 |
T29 |
0 |
65 |
0 |
0 |
T30 |
0 |
3909 |
0 |
0 |
T31 |
0 |
21 |
0 |
0 |
T81 |
0 |
6 |
0 |
0 |
T99 |
0 |
14 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
579230705 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
579230705 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
579230705 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3232 |
3232 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
1893130 |
0 |
0 |
T1 |
44874 |
102 |
0 |
0 |
T2 |
12041 |
0 |
0 |
0 |
T3 |
7235 |
0 |
0 |
0 |
T4 |
88775 |
0 |
0 |
0 |
T5 |
0 |
2864 |
0 |
0 |
T6 |
0 |
28 |
0 |
0 |
T7 |
696192 |
0 |
0 |
0 |
T17 |
7330 |
0 |
0 |
0 |
T18 |
9005 |
0 |
0 |
0 |
T19 |
1469 |
0 |
0 |
0 |
T20 |
8577 |
0 |
0 |
0 |
T22 |
0 |
3 |
0 |
0 |
T27 |
11314 |
0 |
0 |
0 |
T28 |
0 |
57495 |
0 |
0 |
T29 |
0 |
309 |
0 |
0 |
T30 |
0 |
3909 |
0 |
0 |
T31 |
0 |
21 |
0 |
0 |
T81 |
0 |
6 |
0 |
0 |
T99 |
0 |
14 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
579230705 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
579230705 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
579230705 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3232 |
3232 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
18861738 |
0 |
0 |
T1 |
44874 |
127 |
0 |
0 |
T2 |
12041 |
12 |
0 |
0 |
T3 |
7235 |
13 |
0 |
0 |
T4 |
88775 |
40513 |
0 |
0 |
T7 |
696192 |
393 |
0 |
0 |
T17 |
7330 |
12 |
0 |
0 |
T18 |
9005 |
10 |
0 |
0 |
T19 |
1469 |
7 |
0 |
0 |
T20 |
8577 |
717 |
0 |
0 |
T27 |
11314 |
15 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
579230705 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
579230705 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
579230705 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3232 |
3232 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
26194832 |
0 |
0 |
T1 |
44874 |
127 |
0 |
0 |
T2 |
12041 |
12 |
0 |
0 |
T3 |
7235 |
13 |
0 |
0 |
T4 |
88775 |
40513 |
0 |
0 |
T7 |
696192 |
393 |
0 |
0 |
T17 |
7330 |
26 |
0 |
0 |
T18 |
9005 |
38 |
0 |
0 |
T19 |
1469 |
7 |
0 |
0 |
T20 |
8577 |
717 |
0 |
0 |
T27 |
11314 |
15 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
579230705 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
579230705 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579503284 |
579230705 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3232 |
3232 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T5,T22 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T5,T22 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T5,T22 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T5,T22 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T5,T22 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T5,T22 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T5,T22 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T22 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
1847709 |
0 |
0 |
T1 |
44874 |
102 |
0 |
0 |
T2 |
12041 |
0 |
0 |
0 |
T3 |
7235 |
0 |
0 |
0 |
T4 |
88775 |
0 |
0 |
0 |
T5 |
0 |
2864 |
0 |
0 |
T6 |
0 |
28 |
0 |
0 |
T7 |
696192 |
0 |
0 |
0 |
T17 |
7330 |
0 |
0 |
0 |
T18 |
9005 |
0 |
0 |
0 |
T19 |
1469 |
0 |
0 |
0 |
T20 |
8577 |
0 |
0 |
0 |
T22 |
0 |
3 |
0 |
0 |
T27 |
11314 |
0 |
0 |
0 |
T28 |
0 |
57495 |
0 |
0 |
T29 |
0 |
309 |
0 |
0 |
T30 |
0 |
3909 |
0 |
0 |
T31 |
0 |
21 |
0 |
0 |
T81 |
0 |
6 |
0 |
0 |
T99 |
0 |
14 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
577378822 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
577378822 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
577378822 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
1847709 |
0 |
0 |
T1 |
44874 |
102 |
0 |
0 |
T2 |
12041 |
0 |
0 |
0 |
T3 |
7235 |
0 |
0 |
0 |
T4 |
88775 |
0 |
0 |
0 |
T5 |
0 |
2864 |
0 |
0 |
T6 |
0 |
28 |
0 |
0 |
T7 |
696192 |
0 |
0 |
0 |
T17 |
7330 |
0 |
0 |
0 |
T18 |
9005 |
0 |
0 |
0 |
T19 |
1469 |
0 |
0 |
0 |
T20 |
8577 |
0 |
0 |
0 |
T22 |
0 |
3 |
0 |
0 |
T27 |
11314 |
0 |
0 |
0 |
T28 |
0 |
57495 |
0 |
0 |
T29 |
0 |
309 |
0 |
0 |
T30 |
0 |
3909 |
0 |
0 |
T31 |
0 |
21 |
0 |
0 |
T81 |
0 |
6 |
0 |
0 |
T99 |
0 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
| Total | Covered | Percent |
Conditions | 16 | 10 | 62.50 |
Logical | 16 | 10 | 62.50 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T22,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T22,T6 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T22,T6 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T22,T6 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T22,T6 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T22,T6 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T22,T6 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
590008 |
0 |
0 |
T1 |
44874 |
102 |
0 |
0 |
T2 |
12041 |
0 |
0 |
0 |
T3 |
7235 |
0 |
0 |
0 |
T4 |
88775 |
0 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
696192 |
0 |
0 |
0 |
T17 |
7330 |
0 |
0 |
0 |
T18 |
9005 |
0 |
0 |
0 |
T19 |
1469 |
0 |
0 |
0 |
T20 |
8577 |
0 |
0 |
0 |
T22 |
0 |
3 |
0 |
0 |
T27 |
11314 |
0 |
0 |
0 |
T28 |
0 |
12800 |
0 |
0 |
T29 |
0 |
65 |
0 |
0 |
T30 |
0 |
2176 |
0 |
0 |
T31 |
0 |
11 |
0 |
0 |
T99 |
0 |
14 |
0 |
0 |
T100 |
0 |
14 |
0 |
0 |
T101 |
0 |
16 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
577378822 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
577378822 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
577378822 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
590008 |
0 |
0 |
T1 |
44874 |
102 |
0 |
0 |
T2 |
12041 |
0 |
0 |
0 |
T3 |
7235 |
0 |
0 |
0 |
T4 |
88775 |
0 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
696192 |
0 |
0 |
0 |
T17 |
7330 |
0 |
0 |
0 |
T18 |
9005 |
0 |
0 |
0 |
T19 |
1469 |
0 |
0 |
0 |
T20 |
8577 |
0 |
0 |
0 |
T22 |
0 |
3 |
0 |
0 |
T27 |
11314 |
0 |
0 |
0 |
T28 |
0 |
12800 |
0 |
0 |
T29 |
0 |
65 |
0 |
0 |
T30 |
0 |
2176 |
0 |
0 |
T31 |
0 |
11 |
0 |
0 |
T99 |
0 |
14 |
0 |
0 |
T100 |
0 |
14 |
0 |
0 |
T101 |
0 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
| Total | Covered | Percent |
Conditions | 24 | 18 | 75.00 |
Logical | 24 | 18 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T28,T29,T98 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T22,T6 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T22,T6 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T22,T6 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T22,T6 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T22,T6 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T22,T6 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T28,T29,T98 |
1 | 0 | Covered | T1,T22,T6 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T22,T6 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
9 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T22,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T22,T6 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T22,T6 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
1349993 |
0 |
0 |
T1 |
44874 |
102 |
0 |
0 |
T2 |
12041 |
0 |
0 |
0 |
T3 |
7235 |
0 |
0 |
0 |
T4 |
88775 |
0 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
696192 |
0 |
0 |
0 |
T17 |
7330 |
0 |
0 |
0 |
T18 |
9005 |
0 |
0 |
0 |
T19 |
1469 |
0 |
0 |
0 |
T20 |
8577 |
0 |
0 |
0 |
T22 |
0 |
3 |
0 |
0 |
T27 |
11314 |
0 |
0 |
0 |
T28 |
0 |
57495 |
0 |
0 |
T29 |
0 |
309 |
0 |
0 |
T30 |
0 |
2176 |
0 |
0 |
T31 |
0 |
11 |
0 |
0 |
T99 |
0 |
14 |
0 |
0 |
T100 |
0 |
14 |
0 |
0 |
T101 |
0 |
16 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
577378822 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
577378822 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
577378822 |
0 |
0 |
T1 |
44874 |
44787 |
0 |
0 |
T2 |
12041 |
11972 |
0 |
0 |
T3 |
7235 |
7157 |
0 |
0 |
T4 |
88775 |
88678 |
0 |
0 |
T7 |
696192 |
696095 |
0 |
0 |
T17 |
7330 |
7239 |
0 |
0 |
T18 |
9005 |
8907 |
0 |
0 |
T19 |
1469 |
1403 |
0 |
0 |
T20 |
8577 |
8490 |
0 |
0 |
T27 |
11314 |
11227 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577613225 |
1349993 |
0 |
0 |
T1 |
44874 |
102 |
0 |
0 |
T2 |
12041 |
0 |
0 |
0 |
T3 |
7235 |
0 |
0 |
0 |
T4 |
88775 |
0 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
696192 |
0 |
0 |
0 |
T17 |
7330 |
0 |
0 |
0 |
T18 |
9005 |
0 |
0 |
0 |
T19 |
1469 |
0 |
0 |
0 |
T20 |
8577 |
0 |
0 |
0 |
T22 |
0 |
3 |
0 |
0 |
T27 |
11314 |
0 |
0 |
0 |
T28 |
0 |
57495 |
0 |
0 |
T29 |
0 |
309 |
0 |
0 |
T30 |
0 |
2176 |
0 |
0 |
T31 |
0 |
11 |
0 |
0 |
T99 |
0 |
14 |
0 |
0 |
T100 |
0 |
14 |
0 |
0 |
T101 |
0 |
16 |
0 |
0 |