Unified Coverage Report :: Module :: usbdev_reg_top

Module : usbdev_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.52	99.76	98.32			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.52	99.76	98.32			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.52	99.76	98.32			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.79	98.85	98.13	100.00		98.41	93.55

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_avoutbuffer	100.00	100.00
u_avsetupbuffer	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_configin_0_buffer_0	100.00	100.00	100.00			100.00
u_configin_0_pend_0	100.00	100.00	100.00			100.00
u_configin_0_rdy_0	100.00	100.00	100.00			100.00
u_configin_0_sending_0	100.00	100.00	100.00			100.00
u_configin_0_size_0	100.00	100.00	100.00			100.00
u_configin_10_buffer_10	100.00	100.00	100.00			100.00
u_configin_10_pend_10	100.00	100.00	100.00			100.00
u_configin_10_rdy_10	100.00	100.00	100.00			100.00
u_configin_10_sending_10	100.00	100.00	100.00			100.00
u_configin_10_size_10	100.00	100.00	100.00			100.00
u_configin_11_buffer_11	100.00	100.00	100.00			100.00
u_configin_11_pend_11	100.00	100.00	100.00			100.00
u_configin_11_rdy_11	100.00	100.00	100.00			100.00
u_configin_11_sending_11	100.00	100.00	100.00			100.00
u_configin_11_size_11	100.00	100.00	100.00			100.00
u_configin_1_buffer_1	100.00	100.00	100.00			100.00
u_configin_1_pend_1	100.00	100.00	100.00			100.00
u_configin_1_rdy_1	100.00	100.00	100.00			100.00
u_configin_1_sending_1	100.00	100.00	100.00			100.00
u_configin_1_size_1	100.00	100.00	100.00			100.00
u_configin_2_buffer_2	100.00	100.00	100.00			100.00
u_configin_2_pend_2	100.00	100.00	100.00			100.00
u_configin_2_rdy_2	100.00	100.00	100.00			100.00
u_configin_2_sending_2	100.00	100.00	100.00			100.00
u_configin_2_size_2	100.00	100.00	100.00			100.00
u_configin_3_buffer_3	100.00	100.00	100.00			100.00
u_configin_3_pend_3	100.00	100.00	100.00			100.00
u_configin_3_rdy_3	100.00	100.00	100.00			100.00
u_configin_3_sending_3	100.00	100.00	100.00			100.00
u_configin_3_size_3	100.00	100.00	100.00			100.00
u_configin_4_buffer_4	100.00	100.00	100.00			100.00
u_configin_4_pend_4	100.00	100.00	100.00			100.00
u_configin_4_rdy_4	100.00	100.00	100.00			100.00
u_configin_4_sending_4	100.00	100.00	100.00			100.00
u_configin_4_size_4	100.00	100.00	100.00			100.00
u_configin_5_buffer_5	100.00	100.00	100.00			100.00
u_configin_5_pend_5	100.00	100.00	100.00			100.00
u_configin_5_rdy_5	100.00	100.00	100.00			100.00
u_configin_5_sending_5	100.00	100.00	100.00			100.00
u_configin_5_size_5	100.00	100.00	100.00			100.00
u_configin_6_buffer_6	100.00	100.00	100.00			100.00
u_configin_6_pend_6	100.00	100.00	100.00			100.00
u_configin_6_rdy_6	100.00	100.00	100.00			100.00
u_configin_6_sending_6	100.00	100.00	100.00			100.00
u_configin_6_size_6	100.00	100.00	100.00			100.00
u_configin_7_buffer_7	100.00	100.00	100.00			100.00
u_configin_7_pend_7	100.00	100.00	100.00			100.00
u_configin_7_rdy_7	100.00	100.00	100.00			100.00
u_configin_7_sending_7	100.00	100.00	100.00			100.00
u_configin_7_size_7	100.00	100.00	100.00			100.00
u_configin_8_buffer_8	100.00	100.00	100.00			100.00
u_configin_8_pend_8	100.00	100.00	100.00			100.00
u_configin_8_rdy_8	100.00	100.00	100.00			100.00
u_configin_8_sending_8	100.00	100.00	100.00			100.00
u_configin_8_size_8	100.00	100.00	100.00			100.00
u_configin_9_buffer_9	100.00	100.00	100.00			100.00
u_configin_9_pend_9	100.00	100.00	100.00			100.00
u_configin_9_rdy_9	100.00	100.00	100.00			100.00
u_configin_9_sending_9	100.00	100.00	100.00			100.00
u_configin_9_size_9	100.00	100.00	100.00			100.00
u_count_errors_bitstuff	100.00	100.00
u_count_errors_count	100.00	100.00
u_count_errors_crc16	100.00	100.00
u_count_errors_crc5	100.00	100.00
u_count_errors_pid_invalid	100.00	100.00
u_count_errors_rst	100.00	100.00
u_count_in_count	100.00	100.00
u_count_in_endpoints	100.00	100.00
u_count_in_nak	100.00	100.00
u_count_in_nodata	100.00	100.00
u_count_in_rst	100.00	100.00
u_count_in_timeout	100.00	100.00
u_count_nodata_in_count	100.00	100.00
u_count_nodata_in_endpoints	100.00	100.00
u_count_nodata_in_rst	100.00	100.00
u_count_out_count	100.00	100.00
u_count_out_datatog_out	100.00	100.00
u_count_out_drop_avout	100.00	100.00
u_count_out_drop_rx	100.00	100.00
u_count_out_endpoints	100.00	100.00
u_count_out_ign_avsetup	100.00	100.00
u_count_out_rst	100.00	100.00
u_ep_in_enable_enable_0	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_1	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_10	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_11	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_2	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_3	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_4	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_5	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_6	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_7	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_8	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_9	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_0	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_1	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_10	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_11	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_2	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_3	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_4	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_5	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_6	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_7	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_8	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_9	100.00	100.00	100.00			100.00
u_fifo_ctrl0_qe	100.00	100.00				100.00
u_fifo_ctrl_avout_rst	100.00	100.00	100.00			100.00
u_fifo_ctrl_avsetup_rst	100.00	100.00	100.00			100.00
u_fifo_ctrl_rx_rst	100.00	100.00	100.00			100.00
u_in_data_toggle_mask	60.00	60.00
u_in_data_toggle_status	100.00	100.00
u_in_iso_iso_0	100.00	100.00	100.00			100.00
u_in_iso_iso_1	100.00	100.00	100.00			100.00
u_in_iso_iso_10	100.00	100.00	100.00			100.00
u_in_iso_iso_11	100.00	100.00	100.00			100.00
u_in_iso_iso_2	100.00	100.00	100.00			100.00
u_in_iso_iso_3	100.00	100.00	100.00			100.00
u_in_iso_iso_4	100.00	100.00	100.00			100.00
u_in_iso_iso_5	100.00	100.00	100.00			100.00
u_in_iso_iso_6	100.00	100.00	100.00			100.00
u_in_iso_iso_7	100.00	100.00	100.00			100.00
u_in_iso_iso_8	100.00	100.00	100.00			100.00
u_in_iso_iso_9	100.00	100.00	100.00			100.00
u_in_sent_sent_0	100.00	100.00	100.00			100.00
u_in_sent_sent_1	100.00	100.00	100.00			100.00
u_in_sent_sent_10	100.00	100.00	100.00			100.00
u_in_sent_sent_11	100.00	100.00	100.00			100.00
u_in_sent_sent_2	100.00	100.00	100.00			100.00
u_in_sent_sent_3	100.00	100.00	100.00			100.00
u_in_sent_sent_4	100.00	100.00	100.00			100.00
u_in_sent_sent_5	100.00	100.00	100.00			100.00
u_in_sent_sent_6	100.00	100.00	100.00			100.00
u_in_sent_sent_7	100.00	100.00	100.00			100.00
u_in_sent_sent_8	100.00	100.00	100.00			100.00
u_in_sent_sent_9	100.00	100.00	100.00			100.00
u_in_stall_endpoint_0	100.00	100.00	100.00			100.00
u_in_stall_endpoint_1	100.00	100.00	100.00			100.00
u_in_stall_endpoint_10	100.00	100.00	100.00			100.00
u_in_stall_endpoint_11	100.00	100.00	100.00			100.00
u_in_stall_endpoint_2	100.00	100.00	100.00			100.00
u_in_stall_endpoint_3	100.00	100.00	100.00			100.00
u_in_stall_endpoint_4	100.00	100.00	100.00			100.00
u_in_stall_endpoint_5	100.00	100.00	100.00			100.00
u_in_stall_endpoint_6	100.00	100.00	100.00			100.00
u_in_stall_endpoint_7	100.00	100.00	100.00			100.00
u_in_stall_endpoint_8	100.00	100.00	100.00			100.00
u_in_stall_endpoint_9	100.00	100.00	100.00			100.00
u_intr_enable_av_out_empty	100.00	100.00	100.00			100.00
u_intr_enable_av_overflow	100.00	100.00	100.00			100.00
u_intr_enable_av_setup_empty	100.00	100.00	100.00			100.00
u_intr_enable_disconnected	100.00	100.00	100.00			100.00
u_intr_enable_frame	100.00	100.00	100.00			100.00
u_intr_enable_host_lost	100.00	100.00	100.00			100.00
u_intr_enable_link_in_err	100.00	100.00	100.00			100.00
u_intr_enable_link_out_err	100.00	100.00	100.00			100.00
u_intr_enable_link_reset	100.00	100.00	100.00			100.00
u_intr_enable_link_resume	100.00	100.00	100.00			100.00
u_intr_enable_link_suspend	100.00	100.00	100.00			100.00
u_intr_enable_pkt_received	100.00	100.00	100.00			100.00
u_intr_enable_pkt_sent	100.00	100.00	100.00			100.00
u_intr_enable_powered	100.00	100.00	100.00			100.00
u_intr_enable_rx_bitstuff_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_crc_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_full	100.00	100.00	100.00			100.00
u_intr_enable_rx_pid_err	100.00	100.00	100.00			100.00
u_intr_state_av_out_empty	62.59	77.78	50.00			60.00
u_intr_state_av_overflow	100.00	100.00	100.00			100.00
u_intr_state_av_setup_empty	62.59	77.78	50.00			60.00
u_intr_state_disconnected	100.00	100.00	100.00			100.00
u_intr_state_frame	100.00	100.00	100.00			100.00
u_intr_state_host_lost	100.00	100.00	100.00			100.00
u_intr_state_link_in_err	100.00	100.00	100.00			100.00
u_intr_state_link_out_err	100.00	100.00	100.00			100.00
u_intr_state_link_reset	100.00	100.00	100.00			100.00
u_intr_state_link_resume	100.00	100.00	100.00			100.00
u_intr_state_link_suspend	100.00	100.00	100.00			100.00
u_intr_state_pkt_received	62.59	77.78	50.00			60.00
u_intr_state_pkt_sent	62.59	77.78	50.00			60.00
u_intr_state_powered	100.00	100.00	100.00			100.00
u_intr_state_rx_bitstuff_err	100.00	100.00	100.00			100.00
u_intr_state_rx_crc_err	100.00	100.00	100.00			100.00
u_intr_state_rx_full	62.59	77.78	50.00			60.00
u_intr_state_rx_pid_err	100.00	100.00	100.00			100.00
u_intr_test_av_out_empty	100.00	100.00
u_intr_test_av_overflow	100.00	100.00
u_intr_test_av_setup_empty	100.00	100.00
u_intr_test_disconnected	100.00	100.00
u_intr_test_frame	100.00	100.00
u_intr_test_host_lost	100.00	100.00
u_intr_test_link_in_err	100.00	100.00
u_intr_test_link_out_err	100.00	100.00
u_intr_test_link_reset	100.00	100.00
u_intr_test_link_resume	100.00	100.00
u_intr_test_link_suspend	100.00	100.00
u_intr_test_pkt_received	100.00	100.00
u_intr_test_pkt_sent	100.00	100.00
u_intr_test_powered	100.00	100.00
u_intr_test_rx_bitstuff_err	100.00	100.00
u_intr_test_rx_crc_err	100.00	100.00
u_intr_test_rx_full	100.00	100.00
u_intr_test_rx_pid_err	100.00	100.00
u_out_data_toggle_mask	60.00	60.00
u_out_data_toggle_status	100.00	100.00
u_out_iso_iso_0	100.00	100.00	100.00			100.00
u_out_iso_iso_1	100.00	100.00	100.00			100.00
u_out_iso_iso_10	100.00	100.00	100.00			100.00
u_out_iso_iso_11	100.00	100.00	100.00			100.00
u_out_iso_iso_2	100.00	100.00	100.00			100.00
u_out_iso_iso_3	100.00	100.00	100.00			100.00
u_out_iso_iso_4	100.00	100.00	100.00			100.00
u_out_iso_iso_5	100.00	100.00	100.00			100.00
u_out_iso_iso_6	100.00	100.00	100.00			100.00
u_out_iso_iso_7	100.00	100.00	100.00			100.00
u_out_iso_iso_8	100.00	100.00	100.00			100.00
u_out_iso_iso_9	100.00	100.00	100.00			100.00
u_out_stall_endpoint_0	100.00	100.00	100.00			100.00
u_out_stall_endpoint_1	100.00	100.00	100.00			100.00
u_out_stall_endpoint_10	100.00	100.00	100.00			100.00
u_out_stall_endpoint_11	100.00	100.00	100.00			100.00
u_out_stall_endpoint_2	100.00	100.00	100.00			100.00
u_out_stall_endpoint_3	100.00	100.00	100.00			100.00
u_out_stall_endpoint_4	100.00	100.00	100.00			100.00
u_out_stall_endpoint_5	100.00	100.00	100.00			100.00
u_out_stall_endpoint_6	100.00	100.00	100.00			100.00
u_out_stall_endpoint_7	100.00	100.00	100.00			100.00
u_out_stall_endpoint_8	100.00	100.00	100.00			100.00
u_out_stall_endpoint_9	100.00	100.00	100.00			100.00
u_phy_config_eop_single_bit	100.00	100.00	100.00			100.00
u_phy_config_pinflip	100.00	100.00	100.00			100.00
u_phy_config_tx_osc_test_mode	100.00	100.00	100.00			100.00
u_phy_config_tx_use_d_se0	100.00	100.00	100.00			100.00
u_phy_config_usb_ref_disable	100.00	100.00	100.00			100.00
u_phy_config_use_diff_rcvr	100.00	100.00	100.00			100.00
u_phy_pins_drive_d_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dn_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dn_pullup_en_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dp_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dp_pullup_en_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_en	100.00	100.00	100.00			100.00
u_phy_pins_drive_oe_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_rx_enable_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_se0_o	100.00	100.00	100.00			100.00
u_phy_pins_sense_pwr_sense	100.00	100.00
u_phy_pins_sense_rx_d_i	100.00	100.00
u_phy_pins_sense_rx_dn_i	100.00	100.00
u_phy_pins_sense_rx_dp_i	100.00	100.00
u_phy_pins_sense_tx_d_o	100.00	100.00
u_phy_pins_sense_tx_dn_o	100.00	100.00
u_phy_pins_sense_tx_dp_o	100.00	100.00
u_phy_pins_sense_tx_oe_o	100.00	100.00
u_phy_pins_sense_tx_se0_o	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.69	97.14	97.62			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_rxenable_out_out_0	100.00	100.00	100.00			100.00
u_rxenable_out_out_1	100.00	100.00	100.00			100.00
u_rxenable_out_out_10	100.00	100.00	100.00			100.00
u_rxenable_out_out_11	100.00	100.00	100.00			100.00
u_rxenable_out_out_2	100.00	100.00	100.00			100.00
u_rxenable_out_out_3	100.00	100.00	100.00			100.00
u_rxenable_out_out_4	100.00	100.00	100.00			100.00
u_rxenable_out_out_5	100.00	100.00	100.00			100.00
u_rxenable_out_out_6	100.00	100.00	100.00			100.00
u_rxenable_out_out_7	100.00	100.00	100.00			100.00
u_rxenable_out_out_8	100.00	100.00	100.00			100.00
u_rxenable_out_out_9	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_0	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_1	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_10	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_11	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_2	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_3	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_4	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_5	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_6	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_7	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_8	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_9	100.00	100.00	100.00			100.00
u_rxfifo_buffer	100.00	100.00
u_rxfifo_ep	100.00	100.00
u_rxfifo_setup	100.00	100.00
u_rxfifo_size	100.00	100.00
u_set_nak_out_enable_0	100.00	100.00	100.00			100.00
u_set_nak_out_enable_1	100.00	100.00	100.00			100.00
u_set_nak_out_enable_10	100.00	100.00	100.00			100.00
u_set_nak_out_enable_11	100.00	100.00	100.00			100.00
u_set_nak_out_enable_2	100.00	100.00	100.00			100.00
u_set_nak_out_enable_3	100.00	100.00	100.00			100.00
u_set_nak_out_enable_4	100.00	100.00	100.00			100.00
u_set_nak_out_enable_5	100.00	100.00	100.00			100.00
u_set_nak_out_enable_6	100.00	100.00	100.00			100.00
u_set_nak_out_enable_7	100.00	100.00	100.00			100.00
u_set_nak_out_enable_8	100.00	100.00	100.00			100.00
u_set_nak_out_enable_9	100.00	100.00	100.00			100.00
u_socket	98.24	98.75	98.21			96.00	100.00
u_usbctrl0_qe	100.00	100.00				100.00
u_usbctrl_device_address	100.00	100.00	100.00			100.00
u_usbctrl_enable	100.00	100.00	100.00			100.00
u_usbctrl_resume_link_active	100.00	100.00	100.00			100.00
u_usbstat_av_out_depth	100.00	100.00
u_usbstat_av_out_full	100.00	100.00
u_usbstat_av_setup_depth	100.00	100.00
u_usbstat_av_setup_full	100.00	100.00
u_usbstat_frame	100.00	100.00
u_usbstat_host_lost	100.00	100.00
u_usbstat_link_state	100.00	100.00
u_usbstat_rx_depth	100.00	100.00
u_usbstat_rx_empty	100.00	100.00
u_usbstat_sense	100.00	100.00
u_wake_control_cdc	98.13	96.08	96.43			100.00	100.00
u_wake_control_suspend_req	100.00	100.00
u_wake_control_wake_ack	100.00	100.00
u_wake_events_bus_not_idle	62.59	77.78	50.00			60.00
u_wake_events_bus_reset	62.59	77.78	50.00			60.00
u_wake_events_cdc	71.94	90.62	52.94			84.21	60.00
u_wake_events_disconnected	62.59	77.78	50.00			60.00
u_wake_events_module_active	62.59	77.78	50.00			60.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usbdev_reg_top

	Line No.	Total	Covered	Percent
TOTAL		818	816	99.76
ALWAYS	75	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
ALWAYS	132	3	3	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
ALWAYS	789	1	0	0.00
CONT_ASSIGN	816	1	1	100.00
ALWAYS	832	10	10	100.00
CONT_ASSIGN	1849	1	1	100.00
CONT_ASSIGN	1864	1	1	100.00
CONT_ASSIGN	1880	1	1	100.00
CONT_ASSIGN	1896	1	1	100.00
CONT_ASSIGN	1912	1	1	100.00
CONT_ASSIGN	1928	1	1	100.00
CONT_ASSIGN	1944	1	1	100.00
CONT_ASSIGN	1960	1	1	100.00
CONT_ASSIGN	1976	1	1	100.00
CONT_ASSIGN	1992	1	1	100.00
CONT_ASSIGN	2008	1	1	100.00
CONT_ASSIGN	2024	1	1	100.00
CONT_ASSIGN	2040	1	1	100.00
CONT_ASSIGN	2056	1	1	100.00
CONT_ASSIGN	2072	1	1	100.00
CONT_ASSIGN	2088	1	1	100.00
CONT_ASSIGN	2104	1	1	100.00
CONT_ASSIGN	2120	1	1	100.00
CONT_ASSIGN	2136	1	1	100.00
CONT_ASSIGN	2142	1	1	100.00
CONT_ASSIGN	2156	1	1	100.00
CONT_ASSIGN	2224	1	1	100.00
CONT_ASSIGN	3063	1	1	100.00
CONT_ASSIGN	3077	1	1	100.00
CONT_ASSIGN	3083	1	1	100.00
CONT_ASSIGN	3097	1	1	100.00
CONT_ASSIGN	7437	1	1	100.00
CONT_ASSIGN	7452	1	1	100.00
CONT_ASSIGN	7468	1	1	100.00
CONT_ASSIGN	7474	1	1	100.00
CONT_ASSIGN	7489	1	1	100.00
CONT_ASSIGN	7505	1	1	100.00
CONT_ASSIGN	8057	1	1	100.00
CONT_ASSIGN	8072	1	1	100.00
CONT_ASSIGN	8088	1	1	100.00
CONT_ASSIGN	8093	1	0	0.00
CONT_ASSIGN	8241	1	1	100.00
CONT_ASSIGN	8269	1	1	100.00
CONT_ASSIGN	8297	1	1	100.00
CONT_ASSIGN	8305	0	0
CONT_ASSIGN	8306	1	1	100.00
CONT_ASSIGN	8336	1	1	100.00
CONT_ASSIGN	8352	1	1	100.00
CONT_ASSIGN	8368	1	1	100.00
CONT_ASSIGN	8384	1	1	100.00
CONT_ASSIGN	8400	1	1	100.00
CONT_ASSIGN	8416	1	1	100.00
CONT_ASSIGN	8424	0	0
CONT_ASSIGN	8425	1	1	100.00
CONT_ASSIGN	8455	1	1	100.00
CONT_ASSIGN	8471	1	1	100.00
CONT_ASSIGN	8487	1	1	100.00
CONT_ASSIGN	8503	1	1	100.00
CONT_ASSIGN	8519	1	1	100.00
CONT_ASSIGN	8527	0	0
CONT_ASSIGN	8528	1	1	100.00
CONT_ASSIGN	8558	1	1	100.00
CONT_ASSIGN	8574	1	1	100.00
CONT_ASSIGN	8582	0	0
CONT_ASSIGN	8583	1	1	100.00
CONT_ASSIGN	8613	1	1	100.00
CONT_ASSIGN	8629	1	1	100.00
CONT_ASSIGN	8645	1	1	100.00
CONT_ASSIGN	8661	1	1	100.00
CONT_ASSIGN	8677	1	1	100.00
ALWAYS	8683	44	44	100.00
CONT_ASSIGN	8729	1	1	100.00
ALWAYS	8733	1	1	100.00
CONT_ASSIGN	8780	1	1	100.00
CONT_ASSIGN	8782	1	1	100.00
CONT_ASSIGN	8784	1	1	100.00
CONT_ASSIGN	8786	1	1	100.00
CONT_ASSIGN	8788	1	1	100.00
CONT_ASSIGN	8790	1	1	100.00
CONT_ASSIGN	8792	1	1	100.00
CONT_ASSIGN	8794	1	1	100.00
CONT_ASSIGN	8796	1	1	100.00
CONT_ASSIGN	8798	1	1	100.00
CONT_ASSIGN	8800	1	1	100.00
CONT_ASSIGN	8802	1	1	100.00
CONT_ASSIGN	8804	1	1	100.00
CONT_ASSIGN	8806	1	1	100.00
CONT_ASSIGN	8807	1	1	100.00
CONT_ASSIGN	8809	1	1	100.00
CONT_ASSIGN	8811	1	1	100.00
CONT_ASSIGN	8813	1	1	100.00
CONT_ASSIGN	8815	1	1	100.00
CONT_ASSIGN	8817	1	1	100.00
CONT_ASSIGN	8819	1	1	100.00
CONT_ASSIGN	8821	1	1	100.00
CONT_ASSIGN	8823	1	1	100.00
CONT_ASSIGN	8825	1	1	100.00
CONT_ASSIGN	8827	1	1	100.00
CONT_ASSIGN	8829	1	1	100.00
CONT_ASSIGN	8831	1	1	100.00
CONT_ASSIGN	8833	1	1	100.00
CONT_ASSIGN	8835	1	1	100.00
CONT_ASSIGN	8837	1	1	100.00
CONT_ASSIGN	8839	1	1	100.00
CONT_ASSIGN	8841	1	1	100.00
CONT_ASSIGN	8843	1	1	100.00
CONT_ASSIGN	8844	1	1	100.00
CONT_ASSIGN	8846	1	1	100.00
CONT_ASSIGN	8848	1	1	100.00
CONT_ASSIGN	8850	1	1	100.00
CONT_ASSIGN	8852	1	1	100.00
CONT_ASSIGN	8854	1	1	100.00
CONT_ASSIGN	8856	1	1	100.00
CONT_ASSIGN	8858	1	1	100.00
CONT_ASSIGN	8860	1	1	100.00
CONT_ASSIGN	8862	1	1	100.00
CONT_ASSIGN	8864	1	1	100.00
CONT_ASSIGN	8866	1	1	100.00
CONT_ASSIGN	8868	1	1	100.00
CONT_ASSIGN	8870	1	1	100.00
CONT_ASSIGN	8872	1	1	100.00
CONT_ASSIGN	8874	1	1	100.00
CONT_ASSIGN	8876	1	1	100.00
CONT_ASSIGN	8878	1	1	100.00
CONT_ASSIGN	8880	1	1	100.00
CONT_ASSIGN	8881	1	1	100.00
CONT_ASSIGN	8883	1	1	100.00
CONT_ASSIGN	8884	1	1	100.00
CONT_ASSIGN	8886	1	1	100.00
CONT_ASSIGN	8888	1	1	100.00
CONT_ASSIGN	8890	1	1	100.00
CONT_ASSIGN	8891	1	1	100.00
CONT_ASSIGN	8893	1	1	100.00
CONT_ASSIGN	8895	1	1	100.00
CONT_ASSIGN	8897	1	1	100.00
CONT_ASSIGN	8899	1	1	100.00
CONT_ASSIGN	8901	1	1	100.00
CONT_ASSIGN	8903	1	1	100.00
CONT_ASSIGN	8905	1	1	100.00
CONT_ASSIGN	8907	1	1	100.00
CONT_ASSIGN	8909	1	1	100.00
CONT_ASSIGN	8911	1	1	100.00
CONT_ASSIGN	8913	1	1	100.00
CONT_ASSIGN	8915	1	1	100.00
CONT_ASSIGN	8916	1	1	100.00
CONT_ASSIGN	8918	1	1	100.00
CONT_ASSIGN	8920	1	1	100.00
CONT_ASSIGN	8922	1	1	100.00
CONT_ASSIGN	8924	1	1	100.00
CONT_ASSIGN	8926	1	1	100.00
CONT_ASSIGN	8928	1	1	100.00
CONT_ASSIGN	8930	1	1	100.00
CONT_ASSIGN	8932	1	1	100.00
CONT_ASSIGN	8934	1	1	100.00
CONT_ASSIGN	8936	1	1	100.00
CONT_ASSIGN	8938	1	1	100.00
CONT_ASSIGN	8940	1	1	100.00
CONT_ASSIGN	8941	1	1	100.00
CONT_ASSIGN	8942	1	1	100.00
CONT_ASSIGN	8944	1	1	100.00
CONT_ASSIGN	8945	1	1	100.00
CONT_ASSIGN	8947	1	1	100.00
CONT_ASSIGN	8948	1	1	100.00
CONT_ASSIGN	8949	1	1	100.00
CONT_ASSIGN	8951	1	1	100.00
CONT_ASSIGN	8953	1	1	100.00
CONT_ASSIGN	8955	1	1	100.00
CONT_ASSIGN	8957	1	1	100.00
CONT_ASSIGN	8959	1	1	100.00
CONT_ASSIGN	8961	1	1	100.00
CONT_ASSIGN	8963	1	1	100.00
CONT_ASSIGN	8965	1	1	100.00
CONT_ASSIGN	8967	1	1	100.00
CONT_ASSIGN	8969	1	1	100.00
CONT_ASSIGN	8971	1	1	100.00
CONT_ASSIGN	8973	1	1	100.00
CONT_ASSIGN	8974	1	1	100.00
CONT_ASSIGN	8976	1	1	100.00
CONT_ASSIGN	8978	1	1	100.00
CONT_ASSIGN	8980	1	1	100.00
CONT_ASSIGN	8982	1	1	100.00
CONT_ASSIGN	8984	1	1	100.00
CONT_ASSIGN	8986	1	1	100.00
CONT_ASSIGN	8988	1	1	100.00
CONT_ASSIGN	8990	1	1	100.00
CONT_ASSIGN	8992	1	1	100.00
CONT_ASSIGN	8994	1	1	100.00
CONT_ASSIGN	8996	1	1	100.00
CONT_ASSIGN	8998	1	1	100.00
CONT_ASSIGN	8999	1	1	100.00
CONT_ASSIGN	9001	1	1	100.00
CONT_ASSIGN	9003	1	1	100.00
CONT_ASSIGN	9005	1	1	100.00
CONT_ASSIGN	9007	1	1	100.00
CONT_ASSIGN	9009	1	1	100.00
CONT_ASSIGN	9011	1	1	100.00
CONT_ASSIGN	9013	1	1	100.00
CONT_ASSIGN	9015	1	1	100.00
CONT_ASSIGN	9017	1	1	100.00
CONT_ASSIGN	9019	1	1	100.00
CONT_ASSIGN	9021	1	1	100.00
CONT_ASSIGN	9023	1	1	100.00
CONT_ASSIGN	9024	1	1	100.00
CONT_ASSIGN	9026	1	1	100.00
CONT_ASSIGN	9028	1	1	100.00
CONT_ASSIGN	9030	1	1	100.00
CONT_ASSIGN	9032	1	1	100.00
CONT_ASSIGN	9034	1	1	100.00
CONT_ASSIGN	9036	1	1	100.00
CONT_ASSIGN	9038	1	1	100.00
CONT_ASSIGN	9040	1	1	100.00
CONT_ASSIGN	9042	1	1	100.00
CONT_ASSIGN	9044	1	1	100.00
CONT_ASSIGN	9046	1	1	100.00
CONT_ASSIGN	9048	1	1	100.00
CONT_ASSIGN	9049	1	1	100.00
CONT_ASSIGN	9051	1	1	100.00
CONT_ASSIGN	9053	1	1	100.00
CONT_ASSIGN	9055	1	1	100.00
CONT_ASSIGN	9057	1	1	100.00
CONT_ASSIGN	9059	1	1	100.00
CONT_ASSIGN	9061	1	1	100.00
CONT_ASSIGN	9063	1	1	100.00
CONT_ASSIGN	9065	1	1	100.00
CONT_ASSIGN	9067	1	1	100.00
CONT_ASSIGN	9069	1	1	100.00
CONT_ASSIGN	9071	1	1	100.00
CONT_ASSIGN	9073	1	1	100.00
CONT_ASSIGN	9074	1	1	100.00
CONT_ASSIGN	9076	1	1	100.00
CONT_ASSIGN	9078	1	1	100.00
CONT_ASSIGN	9080	1	1	100.00
CONT_ASSIGN	9082	1	1	100.00
CONT_ASSIGN	9084	1	1	100.00
CONT_ASSIGN	9086	1	1	100.00
CONT_ASSIGN	9088	1	1	100.00
CONT_ASSIGN	9090	1	1	100.00
CONT_ASSIGN	9092	1	1	100.00
CONT_ASSIGN	9094	1	1	100.00
CONT_ASSIGN	9096	1	1	100.00
CONT_ASSIGN	9098	1	1	100.00
CONT_ASSIGN	9099	1	1	100.00
CONT_ASSIGN	9101	1	1	100.00
CONT_ASSIGN	9103	1	1	100.00
CONT_ASSIGN	9105	1	1	100.00
CONT_ASSIGN	9107	1	1	100.00
CONT_ASSIGN	9109	1	1	100.00
CONT_ASSIGN	9110	1	1	100.00
CONT_ASSIGN	9112	1	1	100.00
CONT_ASSIGN	9114	1	1	100.00
CONT_ASSIGN	9116	1	1	100.00
CONT_ASSIGN	9118	1	1	100.00
CONT_ASSIGN	9120	1	1	100.00
CONT_ASSIGN	9121	1	1	100.00
CONT_ASSIGN	9123	1	1	100.00
CONT_ASSIGN	9125	1	1	100.00
CONT_ASSIGN	9127	1	1	100.00
CONT_ASSIGN	9129	1	1	100.00
CONT_ASSIGN	9131	1	1	100.00
CONT_ASSIGN	9132	1	1	100.00
CONT_ASSIGN	9134	1	1	100.00
CONT_ASSIGN	9136	1	1	100.00
CONT_ASSIGN	9138	1	1	100.00
CONT_ASSIGN	9140	1	1	100.00
CONT_ASSIGN	9142	1	1	100.00
CONT_ASSIGN	9143	1	1	100.00
CONT_ASSIGN	9145	1	1	100.00
CONT_ASSIGN	9147	1	1	100.00
CONT_ASSIGN	9149	1	1	100.00
CONT_ASSIGN	9151	1	1	100.00
CONT_ASSIGN	9153	1	1	100.00
CONT_ASSIGN	9154	1	1	100.00
CONT_ASSIGN	9156	1	1	100.00
CONT_ASSIGN	9158	1	1	100.00
CONT_ASSIGN	9160	1	1	100.00
CONT_ASSIGN	9162	1	1	100.00
CONT_ASSIGN	9164	1	1	100.00
CONT_ASSIGN	9165	1	1	100.00
CONT_ASSIGN	9167	1	1	100.00
CONT_ASSIGN	9169	1	1	100.00
CONT_ASSIGN	9171	1	1	100.00
CONT_ASSIGN	9173	1	1	100.00
CONT_ASSIGN	9175	1	1	100.00
CONT_ASSIGN	9176	1	1	100.00
CONT_ASSIGN	9178	1	1	100.00
CONT_ASSIGN	9180	1	1	100.00
CONT_ASSIGN	9182	1	1	100.00
CONT_ASSIGN	9184	1	1	100.00
CONT_ASSIGN	9186	1	1	100.00
CONT_ASSIGN	9187	1	1	100.00
CONT_ASSIGN	9189	1	1	100.00
CONT_ASSIGN	9191	1	1	100.00
CONT_ASSIGN	9193	1	1	100.00
CONT_ASSIGN	9195	1	1	100.00
CONT_ASSIGN	9197	1	1	100.00
CONT_ASSIGN	9198	1	1	100.00
CONT_ASSIGN	9200	1	1	100.00
CONT_ASSIGN	9202	1	1	100.00
CONT_ASSIGN	9204	1	1	100.00
CONT_ASSIGN	9206	1	1	100.00
CONT_ASSIGN	9208	1	1	100.00
CONT_ASSIGN	9209	1	1	100.00
CONT_ASSIGN	9211	1	1	100.00
CONT_ASSIGN	9213	1	1	100.00
CONT_ASSIGN	9215	1	1	100.00
CONT_ASSIGN	9217	1	1	100.00
CONT_ASSIGN	9219	1	1	100.00
CONT_ASSIGN	9220	1	1	100.00
CONT_ASSIGN	9222	1	1	100.00
CONT_ASSIGN	9224	1	1	100.00
CONT_ASSIGN	9226	1	1	100.00
CONT_ASSIGN	9228	1	1	100.00
CONT_ASSIGN	9230	1	1	100.00
CONT_ASSIGN	9231	1	1	100.00
CONT_ASSIGN	9233	1	1	100.00
CONT_ASSIGN	9235	1	1	100.00
CONT_ASSIGN	9237	1	1	100.00
CONT_ASSIGN	9239	1	1	100.00
CONT_ASSIGN	9241	1	1	100.00
CONT_ASSIGN	9243	1	1	100.00
CONT_ASSIGN	9245	1	1	100.00
CONT_ASSIGN	9247	1	1	100.00
CONT_ASSIGN	9249	1	1	100.00
CONT_ASSIGN	9251	1	1	100.00
CONT_ASSIGN	9253	1	1	100.00
CONT_ASSIGN	9255	1	1	100.00
CONT_ASSIGN	9256	1	1	100.00
CONT_ASSIGN	9258	1	1	100.00
CONT_ASSIGN	9260	1	1	100.00
CONT_ASSIGN	9262	1	1	100.00
CONT_ASSIGN	9264	1	1	100.00
CONT_ASSIGN	9266	1	1	100.00
CONT_ASSIGN	9268	1	1	100.00
CONT_ASSIGN	9270	1	1	100.00
CONT_ASSIGN	9272	1	1	100.00
CONT_ASSIGN	9274	1	1	100.00
CONT_ASSIGN	9276	1	1	100.00
CONT_ASSIGN	9278	1	1	100.00
CONT_ASSIGN	9280	1	1	100.00
CONT_ASSIGN	9281	1	1	100.00
CONT_ASSIGN	9282	1	1	100.00
CONT_ASSIGN	9284	1	1	100.00
CONT_ASSIGN	9286	1	1	100.00
CONT_ASSIGN	9287	1	1	100.00
CONT_ASSIGN	9288	1	1	100.00
CONT_ASSIGN	9290	1	1	100.00
CONT_ASSIGN	9292	1	1	100.00
CONT_ASSIGN	9293	1	1	100.00
CONT_ASSIGN	9294	1	1	100.00
CONT_ASSIGN	9296	1	1	100.00
CONT_ASSIGN	9298	1	1	100.00
CONT_ASSIGN	9300	1	1	100.00
CONT_ASSIGN	9302	1	1	100.00
CONT_ASSIGN	9304	1	1	100.00
CONT_ASSIGN	9306	1	1	100.00
CONT_ASSIGN	9308	1	1	100.00
CONT_ASSIGN	9310	1	1	100.00
CONT_ASSIGN	9312	1	1	100.00
CONT_ASSIGN	9313	1	1	100.00
CONT_ASSIGN	9315	1	1	100.00
CONT_ASSIGN	9317	1	1	100.00
CONT_ASSIGN	9319	1	1	100.00
CONT_ASSIGN	9321	1	1	100.00
CONT_ASSIGN	9323	1	1	100.00
CONT_ASSIGN	9325	1	1	100.00
CONT_ASSIGN	9326	1	1	100.00
CONT_ASSIGN	9329	1	1	100.00
CONT_ASSIGN	9331	1	1	100.00
CONT_ASSIGN	9333	1	1	100.00
CONT_ASSIGN	9335	1	1	100.00
CONT_ASSIGN	9336	1	1	100.00
CONT_ASSIGN	9337	1	1	100.00
CONT_ASSIGN	9339	1	1	100.00
CONT_ASSIGN	9341	1	1	100.00
CONT_ASSIGN	9343	1	1	100.00
CONT_ASSIGN	9345	1	1	100.00
CONT_ASSIGN	9347	1	1	100.00
CONT_ASSIGN	9349	1	1	100.00
CONT_ASSIGN	9350	1	1	100.00
CONT_ASSIGN	9351	1	1	100.00
CONT_ASSIGN	9353	1	1	100.00
CONT_ASSIGN	9355	1	1	100.00
CONT_ASSIGN	9357	1	1	100.00
CONT_ASSIGN	9359	1	1	100.00
CONT_ASSIGN	9361	1	1	100.00
CONT_ASSIGN	9362	1	1	100.00
CONT_ASSIGN	9363	1	1	100.00
CONT_ASSIGN	9365	1	1	100.00
CONT_ASSIGN	9367	1	1	100.00
CONT_ASSIGN	9368	1	1	100.00
CONT_ASSIGN	9369	1	1	100.00
CONT_ASSIGN	9371	1	1	100.00
CONT_ASSIGN	9373	1	1	100.00
CONT_ASSIGN	9375	1	1	100.00
CONT_ASSIGN	9377	1	1	100.00
CONT_ASSIGN	9379	1	1	100.00
ALWAYS	9383	44	44	100.00
ALWAYS	9431	311	311	100.00
CONT_ASSIGN	9881	1	1	100.00
ALWAYS	9883	4	4	100.00
CONT_ASSIGN	9904	1	1	100.00
CONT_ASSIGN	9905	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
75	1	1
76	1	1
77	1	1
78	1	1
			MISSING_ELSE
84	1	1
102	1	1
103	1	1
105	1	1
106	1	1
132	1	1
138	1	1
139	1	1
			MISSING_ELSE
169	1	1
170	1	1
789	0	1
816	1	1
832	1	1
833	1	1
834	1	1
835	1	1
836	1	1
837	1	1
838	1	1
839	1	1
840	1	1
841	1	1
1849	1	1
1864	1	1
1880	1	1
1896	1	1
1912	1	1
1928	1	1
1944	1	1
1960	1	1
1976	1	1
1992	1	1
2008	1	1
2024	1	1
2040	1	1
2056	1	1
2072	1	1
2088	1	1
2104	1	1
2120	1	1
2136	1	1
2142	1	1
2156	1	1
2224	1	1
3063	1	1
3077	1	1
3083	1	1
3097	1	1
7437	1	1
7452	1	1
7468	1	1
7474	1	1
7489	1	1
7505	1	1
8057	1	1
8072	1	1
8088	1	1
8093	0	1
8241	1	1
8269	1	1
8297	1	1
8305		unreachable
8306	1	1
8336	1	1
8352	1	1
8368	1	1
8384	1	1
8400	1	1
8416	1	1
8424		unreachable
8425	1	1
8455	1	1
8471	1	1
8487	1	1
8503	1	1
8519	1	1
8527		unreachable
8528	1	1
8558	1	1
8574	1	1
8582		unreachable
8583	1	1
8613	1	1
8629	1	1
8645	1	1
8661	1	1
8677	1	1
8683	1	1
8684	1	1
8685	1	1
8686	1	1
8687	1	1
8688	1	1
8689	1	1
8690	1	1
8691	1	1
8692	1	1
8693	1	1
8694	1	1
8695	1	1
8696	1	1
8697	1	1
8698	1	1
8699	1	1
8700	1	1
8701	1	1
8702	1	1
8703	1	1
8704	1	1
8705	1	1
8706	1	1
8707	1	1
8708	1	1
8709	1	1
8710	1	1
8711	1	1
8712	1	1
8713	1	1
8714	1	1
8715	1	1
8716	1	1
8717	1	1
8718	1	1
8719	1	1
8720	1	1
8721	1	1
8722	1	1
8723	1	1
8724	1	1
8725	1	1
8726	1	1
8729	1	1
8733	1	1
8780	1	1
8782	1	1
8784	1	1
8786	1	1
8788	1	1
8790	1	1
8792	1	1
8794	1	1
8796	1	1
8798	1	1
8800	1	1
8802	1	1
8804	1	1
8806	1	1
8807	1	1
8809	1	1
8811	1	1
8813	1	1
8815	1	1
8817	1	1
8819	1	1
8821	1	1
8823	1	1
8825	1	1
8827	1	1
8829	1	1
8831	1	1
8833	1	1
8835	1	1
8837	1	1
8839	1	1
8841	1	1
8843	1	1
8844	1	1
8846	1	1
8848	1	1
8850	1	1
8852	1	1
8854	1	1
8856	1	1
8858	1	1
8860	1	1
8862	1	1
8864	1	1
8866	1	1
8868	1	1
8870	1	1
8872	1	1
8874	1	1
8876	1	1
8878	1	1
8880	1	1
8881	1	1
8883	1	1
8884	1	1
8886	1	1
8888	1	1
8890	1	1
8891	1	1
8893	1	1
8895	1	1
8897	1	1
8899	1	1
8901	1	1
8903	1	1
8905	1	1
8907	1	1
8909	1	1
8911	1	1
8913	1	1
8915	1	1
8916	1	1
8918	1	1
8920	1	1
8922	1	1
8924	1	1
8926	1	1
8928	1	1
8930	1	1
8932	1	1
8934	1	1
8936	1	1
8938	1	1
8940	1	1
8941	1	1
8942	1	1
8944	1	1
8945	1	1
8947	1	1
8948	1	1
8949	1	1
8951	1	1
8953	1	1
8955	1	1
8957	1	1
8959	1	1
8961	1	1
8963	1	1
8965	1	1
8967	1	1
8969	1	1
8971	1	1
8973	1	1
8974	1	1
8976	1	1
8978	1	1
8980	1	1
8982	1	1
8984	1	1
8986	1	1
8988	1	1
8990	1	1
8992	1	1
8994	1	1
8996	1	1
8998	1	1
8999	1	1
9001	1	1
9003	1	1
9005	1	1
9007	1	1
9009	1	1
9011	1	1
9013	1	1
9015	1	1
9017	1	1
9019	1	1
9021	1	1
9023	1	1
9024	1	1
9026	1	1
9028	1	1
9030	1	1
9032	1	1
9034	1	1
9036	1	1
9038	1	1
9040	1	1
9042	1	1
9044	1	1
9046	1	1
9048	1	1
9049	1	1
9051	1	1
9053	1	1
9055	1	1
9057	1	1
9059	1	1
9061	1	1
9063	1	1
9065	1	1
9067	1	1
9069	1	1
9071	1	1
9073	1	1
9074	1	1
9076	1	1
9078	1	1
9080	1	1
9082	1	1
9084	1	1
9086	1	1
9088	1	1
9090	1	1
9092	1	1
9094	1	1
9096	1	1
9098	1	1
9099	1	1
9101	1	1
9103	1	1
9105	1	1
9107	1	1
9109	1	1
9110	1	1
9112	1	1
9114	1	1
9116	1	1
9118	1	1
9120	1	1
9121	1	1
9123	1	1
9125	1	1
9127	1	1
9129	1	1
9131	1	1
9132	1	1
9134	1	1
9136	1	1
9138	1	1
9140	1	1
9142	1	1
9143	1	1
9145	1	1
9147	1	1
9149	1	1
9151	1	1
9153	1	1
9154	1	1
9156	1	1
9158	1	1
9160	1	1
9162	1	1
9164	1	1
9165	1	1
9167	1	1
9169	1	1
9171	1	1
9173	1	1
9175	1	1
9176	1	1
9178	1	1
9180	1	1
9182	1	1
9184	1	1
9186	1	1
9187	1	1
9189	1	1
9191	1	1
9193	1	1
9195	1	1
9197	1	1
9198	1	1
9200	1	1
9202	1	1
9204	1	1
9206	1	1
9208	1	1
9209	1	1
9211	1	1
9213	1	1
9215	1	1
9217	1	1
9219	1	1
9220	1	1
9222	1	1
9224	1	1
9226	1	1
9228	1	1
9230	1	1
9231	1	1
9233	1	1
9235	1	1
9237	1	1
9239	1	1
9241	1	1
9243	1	1
9245	1	1
9247	1	1
9249	1	1
9251	1	1
9253	1	1
9255	1	1
9256	1	1
9258	1	1
9260	1	1
9262	1	1
9264	1	1
9266	1	1
9268	1	1
9270	1	1
9272	1	1
9274	1	1
9276	1	1
9278	1	1
9280	1	1
9281	1	1
9282	1	1
9284	1	1
9286	1	1
9287	1	1
9288	1	1
9290	1	1
9292	1	1
9293	1	1
9294	1	1
9296	1	1
9298	1	1
9300	1	1
9302	1	1
9304	1	1
9306	1	1
9308	1	1
9310	1	1
9312	1	1
9313	1	1
9315	1	1
9317	1	1
9319	1	1
9321	1	1
9323	1	1
9325	1	1
9326	1	1
9329	1	1
9331	1	1
9333	1	1
9335	1	1
9336	1	1
9337	1	1
9339	1	1
9341	1	1
9343	1	1
9345	1	1
9347	1	1
9349	1	1
9350	1	1
9351	1	1
9353	1	1
9355	1	1
9357	1	1
9359	1	1
9361	1	1
9362	1	1
9363	1	1
9365	1	1
9367	1	1
9368	1	1
9369	1	1
9371	1	1
9373	1	1
9375	1	1
9377	1	1
9379	1	1
9383	1	1
9384	1	1
9385	1	1
9386	1	1
9387	1	1
9388	1	1
9389	1	1
9390	1	1
9391	1	1
9392	1	1
9393	1	1
9394	1	1
9395	1	1
9396	1	1
9397	1	1
9398	1	1
9399	1	1
9400	1	1
9401	1	1
9402	1	1
9403	1	1
9404	1	1
9405	1	1
9406	1	1
9407	1	1
9408	1	1
9409	1	1
9410	1	1
9411	1	1
9412	1	1
9413	1	1
9414	1	1
9415	1	1
9416	1	1
9417	1	1
9418	1	1
9419	1	1
9420	1	1
9421	1	1
9422	1	1
9423	1	1
9424	1	1
9425	1	1
9426	1	1
9431	1	1
9432	1	1
9434	1	1
9435	1	1
9436	1	1
9437	1	1
9438	1	1
9439	1	1
9440	1	1
9441	1	1
9442	1	1
9443	1	1
9444	1	1
9445	1	1
9446	1	1
9447	1	1
9448	1	1
9449	1	1
9450	1	1
9451	1	1
9455	1	1
9456	1	1
9457	1	1
9458	1	1
9459	1	1
9460	1	1
9461	1	1
9462	1	1
9463	1	1
9464	1	1
9465	1	1
9466	1	1
9467	1	1
9468	1	1
9469	1	1
9470	1	1
9471	1	1
9472	1	1
9476	1	1
9477	1	1
9478	1	1
9479	1	1
9480	1	1
9481	1	1
9482	1	1
9483	1	1
9484	1	1
9485	1	1
9486	1	1
9487	1	1
9488	1	1
9489	1	1
9490	1	1
9491	1	1
9492	1	1
9493	1	1
9497	1	1
9501	1	1
9502	1	1
9503	1	1
9507	1	1
9508	1	1
9509	1	1
9510	1	1
9511	1	1
9512	1	1
9513	1	1
9514	1	1
9515	1	1
9516	1	1
9517	1	1
9518	1	1
9522	1	1
9523	1	1
9524	1	1
9525	1	1
9526	1	1
9527	1	1
9528	1	1
9529	1	1
9530	1	1
9531	1	1
9532	1	1
9533	1	1
9537	1	1
9538	1	1
9539	1	1
9540	1	1
9541	1	1
9542	1	1
9543	1	1
9544	1	1
9545	1	1
9546	1	1
9550	1	1
9554	1	1
9558	1	1
9559	1	1
9560	1	1
9561	1	1
9565	1	1
9566	1	1
9567	1	1
9568	1	1
9569	1	1
9570	1	1
9571	1	1
9572	1	1
9573	1	1
9574	1	1
9575	1	1
9576	1	1
9580	1	1
9581	1	1
9582	1	1
9583	1	1
9584	1	1
9585	1	1
9586	1	1
9587	1	1
9588	1	1
9589	1	1
9590	1	1
9591	1	1
9595	1	1
9596	1	1
9597	1	1
9598	1	1
9599	1	1
9600	1	1
9601	1	1
9602	1	1
9603	1	1
9604	1	1
9605	1	1
9606	1	1
9610	1	1
9611	1	1
9612	1	1
9613	1	1
9614	1	1
9615	1	1
9616	1	1
9617	1	1
9618	1	1
9619	1	1
9620	1	1
9621	1	1
9625	1	1
9626	1	1
9627	1	1
9628	1	1
9629	1	1
9630	1	1
9631	1	1
9632	1	1
9633	1	1
9634	1	1
9635	1	1
9636	1	1
9640	1	1
9641	1	1
9642	1	1
9643	1	1
9644	1	1
9645	1	1
9646	1	1
9647	1	1
9648	1	1
9649	1	1
9650	1	1
9651	1	1
9655	1	1
9656	1	1
9657	1	1
9658	1	1
9659	1	1
9663	1	1
9664	1	1
9665	1	1
9666	1	1
9667	1	1
9671	1	1
9672	1	1
9673	1	1
9674	1	1
9675	1	1
9679	1	1
9680	1	1
9681	1	1
9682	1	1
9683	1	1
9687	1	1
9688	1	1
9689	1	1
9690	1	1
9691	1	1
9695	1	1
9696	1	1
9697	1	1
9698	1	1
9699	1	1
9703	1	1
9704	1	1
9705	1	1
9706	1	1
9707	1	1
9711	1	1
9712	1	1
9713	1	1
9714	1	1
9715	1	1
9719	1	1
9720	1	1
9721	1	1
9722	1	1
9723	1	1
9727	1	1
9728	1	1
9729	1	1
9730	1	1
9731	1	1
9735	1	1
9736	1	1
9737	1	1
9738	1	1
9739	1	1
9743	1	1
9744	1	1
9745	1	1
9746	1	1
9747	1	1
9751	1	1
9752	1	1
9753	1	1
9754	1	1
9755	1	1
9756	1	1
9757	1	1
9758	1	1
9759	1	1
9760	1	1
9761	1	1
9762	1	1
9766	1	1
9767	1	1
9768	1	1
9769	1	1
9770	1	1
9771	1	1
9772	1	1
9773	1	1
9774	1	1
9775	1	1
9776	1	1
9777	1	1
9781	1	1
9782	1	1
9786	1	1
9787	1	1
9791	1	1
9792	1	1
9793	1	1
9794	1	1
9795	1	1
9796	1	1
9797	1	1
9798	1	1
9799	1	1
9803	1	1
9804	1	1
9805	1	1
9806	1	1
9807	1	1
9808	1	1
9809	1	1
9810	1	1
9811	1	1
9815	1	1
9816	1	1
9817	1	1
9818	1	1
9819	1	1
9820	1	1
9824	1	1
9827	1	1
9830	1	1
9831	1	1
9832	1	1
9836	1	1
9837	1	1
9838	1	1
9839	1	1
9840	1	1
9841	1	1
9842	1	1
9846	1	1
9847	1	1
9848	1	1
9849	1	1
9850	1	1
9851	1	1
9855	1	1
9856	1	1
9857	1	1
9861	1	1
9862	1	1
9863	1	1
9864	1	1
9865	1	1
9866	1	1
9881	1	1
9883	1	1
9884	1	1
9886	1	1
9889	1	1
9904	1	1
9905	1	1

---

Cond Coverage for Module : usbdev_reg_top

	Total	Covered	Percent
Conditions	477	469	98.32
Logical	477	469	98.32
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
65-9287	99.05
9288-9881	93.10

---

Branch Coverage for Module : usbdev_reg_top

	Line No.	Total	Covered	Percent
Branches		56	56	100.00
TERNARY	8729	2	2	100.00
IF	75	3	3	100.00
TERNARY	132	2	2	100.00
IF	138	2	2	100.00
CASE	9432	44	44	100.00
CASE	9884	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	8729	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	75	if ((!rst_ni))
-2-:	77	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T212,T213,T214
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	132	((tl_i.a_address[(AW - 1):0] inside {[2048:4095]})) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T241,T246,T247
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	9432	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
addr_hit[35]	Covered	T1,T2,T3
addr_hit[36]	Covered	T1,T2,T3
addr_hit[37]	Covered	T1,T2,T3
addr_hit[38]	Covered	T1,T2,T3
addr_hit[39]	Covered	T1,T2,T3
addr_hit[40]	Covered	T1,T2,T3
addr_hit[41]	Covered	T1,T2,T3
addr_hit[42]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	9884	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[36]	Covered	T1,T2,T3
addr_hit[37]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	579503284	18593397	0	0
reAfterRv	579503284	18593397	0	0
rePulse	579503284	18304524	0	0
wePulse	579503284	288873	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	579503284	18593397	0	0
T1	44874	127	0	0
T2	12041	12	0	0
T3	7235	13	0	0
T4	88775	40513	0	0
T7	696192	393	0	0
T17	7330	12	0	0
T18	9005	10	0	0
T19	1469	7	0	0
T20	8577	717	0	0
T27	11314	15	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	579503284	18593397	0	0
T1	44874	127	0	0
T2	12041	12	0	0
T3	7235	13	0	0
T4	88775	40513	0	0
T7	696192	393	0	0
T17	7330	12	0	0
T18	9005	10	0	0
T19	1469	7	0	0
T20	8577	717	0	0
T27	11314	15	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	579503284	18304524	0	0
T1	44874	50	0	0
T2	12041	3	0	0
T3	7235	4	0	0
T4	88775	40350	0	0
T7	696192	380	0	0
T17	7330	5	0	0
T18	9005	2	0	0
T19	1469	5	0	0
T20	8577	135	0	0
T27	11314	4	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	579503284	288873	0	0
T1	44874	77	0	0
T2	12041	9	0	0
T3	7235	9	0	0
T4	88775	163	0	0
T7	696192	13	0	0
T17	7330	7	0	0
T18	9005	8	0	0
T19	1469	2	0	0
T20	8577	582	0	0
T27	11314	11	0	0