Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9426452	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9990564

1

T1

9

T2

7

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	18771019	1			T1	6		T2	5		T3	2
values[0x0]	322250	1			T1	5		T2	6		T3	2
values[0x1]	323747	1			T1	5		T2	5		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7489964	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

11927052

1

T1

13

T2

9

T3

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57689	1			T38	1		T31	2		T33	3
valid_sources[0x01]	71383	1			T4	46		T5	50		T91	3
valid_sources[0x02]	58128	1			T31	1		T35	1		T36	1
valid_sources[0x03]	56260	1			T31	1		T33	3		T4	48
valid_sources[0x04]	71484	1			T32	1		T35	1		T36	2
valid_sources[0x05]	59088	1			T32	3		T36	1		T4	49
valid_sources[0x06]	57622	1			T31	2		T4	52		T5	42
valid_sources[0x07]	71219	1			T35	1		T4	44		T5	29
valid_sources[0x08]	56814	1			T2	1		T4	48		T5	4
valid_sources[0x09]	137836	1			T31	2		T32	1		T35	1
valid_sources[0x0a]	56634	1			T36	2		T4	52		T5	45
valid_sources[0x0b]	56393	1			T32	1		T35	1		T4	45
valid_sources[0x0c]	56102	1			T31	1		T4	59		T76	2
valid_sources[0x0d]	56478	1			T32	1		T35	1		T36	2
valid_sources[0x0e]	80186	1			T32	1		T4	31		T76	1
valid_sources[0x0f]	57029	1			T31	1		T4	41		T5	10
valid_sources[0x10]	79357	1			T35	1		T4	51		T5	18
valid_sources[0x11]	74901	1			T4	41		T5	3		T91	2
valid_sources[0x12]	69467	1			T31	1		T35	2		T36	1
valid_sources[0x13]	76409	1			T36	1		T4	47		T5	32
valid_sources[0x14]	133886	1			T32	2		T4	47		T5	43
valid_sources[0x15]	77355	1			T31	1		T32	2		T35	2
valid_sources[0x16]	57429	1			T4	46		T5	34		T63	73
valid_sources[0x17]	134512	1			T2	1		T32	3		T33	1
valid_sources[0x18]	66539	1			T31	2		T35	1		T4	37
valid_sources[0x19]	58526	1			T31	1		T35	1		T4	57
valid_sources[0x1a]	90187	1			T4	41		T5	89		T91	3
valid_sources[0x1b]	57294	1			T32	1		T4	65		T5	24
valid_sources[0x1c]	57184	1			T32	1		T35	1		T4	46
valid_sources[0x1d]	93354	1			T36	1		T4	46		T5	53
valid_sources[0x1e]	56526	1			T1	2		T31	1		T35	4
valid_sources[0x1f]	57620	1			T4	49		T5	58		T91	3
valid_sources[0x20]	57865	1			T32	1		T4	35		T5	70
valid_sources[0x21]	62967	1			T4	59		T5	53		T91	1
valid_sources[0x22]	56787	1			T32	1		T4	34		T5	91
valid_sources[0x23]	101347	1			T31	3		T35	1		T4	64
valid_sources[0x24]	58982	1			T32	1		T35	1		T36	1
valid_sources[0x25]	56699	1			T4	53		T5	28		T91	7
valid_sources[0x26]	56525	1			T31	1		T32	2		T35	1
valid_sources[0x27]	69690	1			T33	2		T35	3		T36	1
valid_sources[0x28]	73260	1			T2	1		T32	1		T36	1
valid_sources[0x29]	57074	1			T2	1		T36	2		T4	49
valid_sources[0x2a]	57014	1			T32	1		T36	1		T4	43
valid_sources[0x2b]	73686	1			T32	2		T35	1		T36	1
valid_sources[0x2c]	57324	1			T34	2		T4	44		T5	43
valid_sources[0x2d]	81765	1			T31	2		T32	1		T33	3
valid_sources[0x2e]	56244	1			T2	3		T36	3		T4	46
valid_sources[0x2f]	69206	1			T32	1		T36	1		T4	61
valid_sources[0x30]	57237	1			T32	2		T33	1		T4	40
valid_sources[0x31]	78847	1			T35	1		T4	52		T5	71
valid_sources[0x32]	148491	1			T38	1		T32	2		T4	45
valid_sources[0x33]	56641	1			T31	3		T36	1		T4	55
valid_sources[0x34]	76616	1			T33	3		T35	2		T4	39
valid_sources[0x35]	57316	1			T35	1		T4	41		T5	61
valid_sources[0x36]	76647	1			T1	1		T32	1		T33	1
valid_sources[0x37]	57885	1			T32	1		T33	2		T4	45
valid_sources[0x38]	65006	1			T38	2		T31	3		T33	2
valid_sources[0x39]	69005	1			T36	1		T4	55		T5	17
valid_sources[0x3a]	56422	1			T32	1		T4	44		T5	42
valid_sources[0x3b]	57567	1			T33	3		T4	44		T5	19
valid_sources[0x3c]	88931	1			T31	1		T33	3		T4	34
valid_sources[0x3d]	56986	1			T31	1		T4	37		T5	49
valid_sources[0x3e]	57552	1			T4	48		T5	47		T91	1
valid_sources[0x3f]	57341	1			T33	1		T36	1		T4	43
valid_sources[0x40]	57217	1			T31	2		T4	52		T5	68
valid_sources[0x41]	57214	1			T35	2		T4	52		T5	32
valid_sources[0x42]	56298	1			T36	1		T4	48		T5	44
valid_sources[0x43]	56250	1			T38	1		T31	2		T35	1
valid_sources[0x44]	95204	1			T38	1		T31	1		T4	45
valid_sources[0x45]	55823	1			T35	1		T95	1		T4	52
valid_sources[0x46]	99391	1			T31	1		T36	1		T4	41
valid_sources[0x47]	62349	1			T36	1		T4	31		T5	44
valid_sources[0x48]	72459	1			T4	41		T5	17		T91	2
valid_sources[0x49]	58249	1			T35	2		T4	34		T5	27
valid_sources[0x4a]	57055	1			T95	1		T4	67		T5	37
valid_sources[0x4b]	147531	1			T31	1		T35	1		T36	1
valid_sources[0x4c]	58366	1			T32	2		T35	4		T36	1
valid_sources[0x4d]	59563	1			T38	1		T31	1		T33	1
valid_sources[0x4e]	57922	1			T1	3		T39	47		T4	57
valid_sources[0x4f]	91127	1			T31	1		T36	1		T4	46
valid_sources[0x50]	180021	1			T32	1		T4	54		T5	36
valid_sources[0x51]	58630	1			T31	3		T4	42		T5	10
valid_sources[0x52]	185445	1			T35	1		T4	42		T5	7
valid_sources[0x53]	58006	1			T35	1		T36	2		T4	37
valid_sources[0x54]	56792	1			T35	1		T4	43		T5	8
valid_sources[0x55]	64941	1			T36	1		T4	48		T5	12
valid_sources[0x56]	156949	1			T33	1		T4	45		T5	11
valid_sources[0x57]	58040	1			T31	1		T4	47		T5	8
valid_sources[0x58]	57694	1			T4	58		T5	45		T91	3
valid_sources[0x59]	79830	1			T4	31		T5	44		T77	1
valid_sources[0x5a]	56431	1			T31	1		T36	1		T4	39
valid_sources[0x5b]	64848	1			T35	1		T4	59		T5	39
valid_sources[0x5c]	57396	1			T35	1		T36	1		T4	52
valid_sources[0x5d]	67631	1			T36	1		T4	48		T5	30
valid_sources[0x5e]	87780	1			T31	2		T32	3		T33	2
valid_sources[0x5f]	56268	1			T32	2		T33	1		T36	1
valid_sources[0x60]	73909	1			T2	3		T35	1		T4	40
valid_sources[0x61]	109692	1			T33	4		T35	1		T4	46
valid_sources[0x62]	78543	1			T2	1		T31	1		T32	1
valid_sources[0x63]	79207	1			T31	2		T32	2		T36	1
valid_sources[0x64]	129044	1			T31	1		T33	3		T4	55
valid_sources[0x65]	143441	1			T32	2		T4	50		T5	38
valid_sources[0x66]	172775	1			T4	54		T5	24		T62	1
valid_sources[0x67]	55860	1			T1	4		T31	1		T32	1
valid_sources[0x68]	120443	1			T32	1		T33	2		T36	1
valid_sources[0x69]	72981	1			T36	2		T4	53		T5	59
valid_sources[0x6a]	181098	1			T33	2		T34	4		T4	44
valid_sources[0x6b]	144302	1			T4	44		T5	67		T91	5
valid_sources[0x6c]	57186	1			T4	44		T5	55		T91	5
valid_sources[0x6d]	96673	1			T31	2		T32	1		T36	1
valid_sources[0x6e]	57239	1			T4	41		T5	58		T63	83
valid_sources[0x6f]	57662	1			T31	2		T32	1		T4	46
valid_sources[0x70]	57524	1			T38	1		T32	2		T33	1
valid_sources[0x71]	58734	1			T4	60		T5	28		T91	2
valid_sources[0x72]	56826	1			T31	3		T33	2		T36	1
valid_sources[0x73]	71160	1			T33	1		T36	1		T4	45
valid_sources[0x74]	87559	1			T4	45		T5	32		T91	2
valid_sources[0x75]	58356	1			T32	3		T4	60		T5	58
valid_sources[0x76]	55996	1			T4	38		T5	35		T91	1
valid_sources[0x77]	56929	1			T33	2		T35	1		T4	34
valid_sources[0x78]	88271	1			T4	58		T5	18		T91	2
valid_sources[0x79]	69686	1			T35	4		T36	1		T4	44
valid_sources[0x7a]	67059	1			T32	1		T36	1		T4	37
valid_sources[0x7b]	57125	1			T31	2		T36	2		T4	35
valid_sources[0x7c]	57452	1			T32	1		T4	43		T76	1
valid_sources[0x7d]	148642	1			T29	3		T31	2		T4	53
valid_sources[0x7e]	57808	1			T31	1		T4	43		T5	39
valid_sources[0x7f]	125865	1			T38	1		T31	1		T4	30
valid_sources[0x80]	61823	1			T39	13		T31	1		T32	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9466243

1

T1

3

T2

1

T38

2

values[0x0]

all_enables

biggest_size

270558

1

T1

5

T2

3

T3

2

values[0x1]

all_enables

biggest_size

253763

1

T1

1

T2

3

T3

1