Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

9440757

1

T1

7

T2

9

T3

6

full_word

9991509

1

T1

9

T2

7

T3

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	19431916	1			T1	16		T2	16		T3	9
auto[TlIntgErrCmd]	117	1			T215	2		T217	3		T259	6
auto[TlIntgErrData]	110	1			T215	4		T217	2		T259	6
auto[TlIntgErrBoth]	123	1			T215	4		T217	5		T259	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18772954

1

T1

6

T2

5

T3

2

auto[1]

659312

1

T1

10

T2

11

T3

7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9306375	1			T1	3		T2	4		T3	2
auto[TlIntgErrNone]	partial	auto[1]	134051	1			T1	4		T2	5		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	9466419	1			T1	3		T2	1		T38	2
auto[TlIntgErrNone]	full_word	auto[1]	525071	1			T1	6		T2	6		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T215	2		T217	1		T259	3
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T217	2		T259	3		T264	5
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T281	1		T347	1		T348	1
auto[TlIntgErrData]	partial	auto[0]	56	1			T215	2		T259	4		T264	5
auto[TlIntgErrData]	partial	auto[1]	45	1			T215	2		T217	2		T259	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T282	1		T283	1		T349	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T282	1		T350	1		T351	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T215	1		T217	2		T259	3
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T215	3		T217	3		T259	5
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T284	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T283	1		T352	1		T350	1