Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	610974013	11057	0	0
ep_in_enable_rd_A	610974013	3942	0	0
ep_out_enable_rd_A	610974013	3745	0	0
in_iso_rd_A	610974013	3322	0	0
intr_enable_rd_A	610974013	5595	0	0
out_iso_rd_A	610974013	3982	0	0
phy_config_rd_A	610974013	2487	0	0
phy_pins_drive_rd_A	610974013	2877	0	0
rxenable_setup_rd_A	610974013	3947	0	0
set_nak_out_rd_A	610974013	4010	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	11057	0	0
T215	23676	1	0	0
T216	10310	11	0	0
T217	23094	4	0	0
T257	5150	502	0	0
T258	3670	4	0	0
T259	47064	4	0	0
T264	64284	4	0	0
T265	8399	13	0	0
T278	12610	12	0	0
T281	98287	3	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	3942	0	0
T215	23676	183	0	0
T216	10310	52	0	0
T217	23094	230	0	0
T260	6329	25	0	0
T265	8399	40	0	0
T278	12610	18	0	0
T281	98287	412	0	0
T282	65757	349	0	0
T300	3701	41	0	0
T313	9834	8	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	3745	0	0
T215	23676	122	0	0
T216	10310	55	0	0
T217	23094	318	0	0
T260	6329	10	0	0
T265	8399	50	0	0
T278	12610	67	0	0
T281	98287	592	0	0
T282	65757	229	0	0
T300	3701	35	0	0
T313	9834	54	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	3322	0	0
T215	23676	153	0	0
T216	10310	90	0	0
T217	23094	147	0	0
T260	6329	3	0	0
T265	8399	18	0	0
T278	12610	49	0	0
T281	98287	386	0	0
T282	65757	330	0	0
T300	3701	66	0	0
T313	9834	39	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	5595	0	0
T215	23676	207	0	0
T216	10310	140	0	0
T217	23094	180	0	0
T224	2669	22	0	0
T260	6329	46	0	0
T265	8399	79	0	0
T300	3701	8	0	0
T313	9834	39	0	0
T319	2095	24	0	0
T320	2304	29	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	3982	0	0
T215	23676	93	0	0
T216	10310	72	0	0
T217	23094	202	0	0
T260	6329	8	0	0
T265	8399	6	0	0
T278	12610	60	0	0
T281	98287	571	0	0
T282	65757	256	0	0
T300	3701	8	0	0
T313	9834	41	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	2487	0	0
T215	23676	72	0	0
T216	10310	46	0	0
T217	23094	163	0	0
T260	6329	8	0	0
T265	8399	17	0	0
T278	12610	56	0	0
T281	98287	277	0	0
T282	65757	127	0	0
T300	3701	8	0	0
T313	9834	52	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	2877	0	0
T215	23676	112	0	0
T216	10310	59	0	0
T217	23094	133	0	0
T260	6329	17	0	0
T265	8399	29	0	0
T278	12610	48	0	0
T281	98287	224	0	0
T282	65757	178	0	0
T300	3701	47	0	0
T313	9834	77	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	3947	0	0
T215	23676	151	0	0
T216	10310	12	0	0
T217	23094	362	0	0
T260	6329	43	0	0
T265	8399	17	0	0
T278	12610	113	0	0
T281	98287	548	0	0
T282	65757	267	0	0
T300	3701	30	0	0
T313	9834	50	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	4010	0	0
T215	23676	102	0	0
T216	10310	11	0	0
T217	23094	245	0	0
T260	6329	23	0	0
T265	8399	13	0	0
T278	12610	92	0	0
T281	98287	455	0	0
T282	65757	351	0	0
T300	3701	5	0	0
T313	9834	42	0	0