Unified Coverage Report :: Module :: usbdev_linkstate

Module : usbdev_linkstate

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.25	97.12	92.75		88.89	87.50	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_linkstate.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_impl.u_usbdev_linkstate	95.15	97.12	95.52		88.89	94.23	100.00

---

Module Instance : tb.dut.usbdev_impl.u_usbdev_linkstate

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.15	97.12	95.52		88.89	94.23	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.65	97.66	96.39		88.89	95.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.40	100.00	97.59			100.00	100.00	usbdev_impl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
filter_pwr_sense	100.00	100.00	100.00			100.00
filter_se0	100.00	100.00	100.00			100.00

Line Coverage for Module : usbdev_linkstate

	Line No.	Total	Covered	Percent
TOTAL		104	101	97.12
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
ALWAYS	139	34	31	91.18
ALWAYS	231	3	3	100.00
ALWAYS	245	18	18	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	292	5	5	100.00
ALWAYS	307	16	16	100.00
ALWAYS	348	5	5	100.00
CONT_ASSIGN	365	1	1	100.00
ALWAYS	367	6	6	100.00
CONT_ASSIGN	378	1	1	100.00
ALWAYS	380	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_linkstate.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_linkstate.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
92	1	1
93	1	1
94	1	1
96	1	1
99	1	1
105	1	1
133	1	1
135	1	1
139	1	1
140	1	1
144	1	1
145	1	1
147	1	1
150	1	1
151	1	1
			==> MISSING_ELSE
156	1	1
157	1	1
158	1	1
161	1	1
162	1	1
163	1	1
			MISSING_ELSE
168	1	1
169	0	1
170	1	1
171	1	1
172	1	1
			MISSING_ELSE
184	1	1
185	1	1
186	1	1
			MISSING_ELSE
195	1	1
196	1	1
197	1	1
198	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
212	1	1
213	0	1
214	0	1
215	1	1
216	1	1
			MISSING_ELSE
231	1	1
232	1	1
234	1	1
245	1	1
246	1	1
247	1	1
248	1	1
250	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
261	1	1
262	1	1
264	1	1
265	1	1
266	1	1
268	1	1
			MISSING_ELSE
276	1	1
277	1	1
278	1	1
			MISSING_ELSE
280	1	1
289	1	1
292	1	1
293	1	1
294	1	1
296	1	1
297	1	1
307	1	1
308	1	1
309	1	1
311	1	1
314	1	1
315	1	1
316	1	1
			MISSING_ELSE
322	1	1
323	1	1
324	1	1
325	1	1
326	1	1
327	1	1
329	1	1
			MISSING_ELSE
336	1	1
337	1	1
			==> MISSING_ELSE
348	1	1
349	1	1
350	1	1
352	1	1
353	1	1
365	1	1
367	1	1
368	1	1
370	1	1
371	1	1
372	1	1
373	1	1
			MISSING_ELSE
378	1	1
380	1	1
381	1	1
383	1	1
384	1	1
385	1	1
386	1	1
			MISSING_ELSE

---

Cond Coverage for Module : usbdev_linkstate

	Total	Covered	Percent
Conditions	69	64	92.75
Logical	69	64	92.75
Non-Logical	0	0
Event	0	0

 LINE       92
 EXPRESSION (link_state_q == LinkDisconnected)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       94
 EXPRESSION ((link_state_q == LinkSuspended) || (link_state_q == LinkPoweredSuspended))
             ---------------1---------------    -------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T38,T11
1	0	Covered	T5,T46,T70

 LINE       94
 SUB-EXPRESSION (link_state_q == LinkSuspended)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T46,T70

 LINE       94
 SUB-EXPRESSION (link_state_q == LinkPoweredSuspended)
                -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T38,T11

 LINE       96
 EXPRESSION ((link_state_q == LinkActive) || (link_state_q == LinkActiveNoSOF))
             --------------1-------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T21,T9

 LINE       96
 SUB-EXPRESSION (link_state_q == LinkActive)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T21,T9

 LINE       96
 SUB-EXPRESSION (link_state_q == LinkActiveNoSOF)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       105
 EXPRESSION ((usb_dn_i == 1'b0) & (usb_dp_i == 1'b0) & (usb_oe_i == 1'b0))
             ---------1--------   ---------2--------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T39
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T3,T29
1	1	1	Covered	T1,T2,T3

 LINE       105
 SUB-EXPRESSION (usb_dn_i == 1'b0)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       105
 SUB-EXPRESSION (usb_dp_i == 1'b0)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       105
 SUB-EXPRESSION (usb_oe_i == 1'b0)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       135
 EXPRESSION (see_pwr_sense ? ((link_state_q == LinkPowered) | link_active_o) : 1'b0)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       135
 SUB-EXPRESSION ((link_state_q == LinkPowered) | link_active_o)
                 --------------1--------------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       135
 SUB-EXPRESSION (link_state_q == LinkPowered)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (((!see_pwr_sense)) || ((!usb_pullup_en_i)))
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T38
1	0	Covered	T3,T39,T29

 LINE       150
 EXPRESSION (see_pwr_sense & usb_pullup_en_i)
             ------1------   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       184
 EXPRESSION (rx_j_det_i | ev_reset)
             -----1----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T46,T70
0	1	Not Covered
1	0	Covered	T5,T46,T70

 LINE       265
 EXPRESSION (link_rst_timer_q == RESET_TIMEOUT)
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       315
 EXPRESSION (((!ev_bus_active)) && monitor_inac)
             ---------1--------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T38,T5
1	1	Covered	T1,T2,T3

 LINE       322
 EXPRESSION (ev_bus_active || ((!monitor_inac)))
             ------1------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T38,T6
1	0	Covered	T1,T2,T3

 LINE       325
 EXPRESSION (link_inac_timer_q == SUSPEND_TIMEOUT)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T38,T5

 LINE       336
 EXPRESSION (ev_bus_active || ((!monitor_inac)))
             ------1------    --------2--------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T38,T5
1	0	Not Covered

 LINE       370
 EXPRESSION (sof_detected_i || ((!link_active_o)) || link_reset)
             -------1------    ---------2--------    -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T7,T21,T9

 LINE       372
 EXPRESSION (sof_missed_o && ((!host_lost_o)))
             ------1-----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T100
1	1	Covered	T4,T5,T63

 LINE       378
 EXPRESSION (missing_sof_timer == SOF_TIMEOUT)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T63

 LINE       383
 EXPRESSION (sof_missed_o || sof_detected_i || ((!link_active_o)) || link_reset)
             ------1-----    -------2------    ---------3--------    -----4----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	1	0	0	Covered	T7,T21,T9
1	0	0	0	Covered	T4,T5,T63

---

FSM Coverage for Module : usbdev_linkstate

Summary for FSM :: link_state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	19	16	84.21
Sequences	0	0

State, Transition and Sequence Details for FSM :: link_state_q

---

states	Line No.	Covered	Tests
LinkActive	198	Covered	T7,T21,T9
LinkActiveNoSOF	157	Covered	T1,T2,T3
LinkDisconnected	145	Covered	T1,T2,T3
LinkPowered	151	Covered	T1,T2,T3
LinkPoweredSuspended	163	Covered	T1,T38,T11
LinkResuming	161	Covered	T5,T46,T70
LinkSuspended	196	Covered	T5,T46,T70

transitions	Line No.	Covered	Tests
LinkActive->LinkActiveNoSOF	207	Covered	T21,T9,T12
LinkActive->LinkDisconnected	145	Covered	T67,T68,T69
LinkActive->LinkSuspended	205	Covered	T7,T10,T101
LinkActiveNoSOF->LinkActive	198	Covered	T7,T21,T9
LinkActiveNoSOF->LinkDisconnected	145	Covered	T1,T38,T31
LinkActiveNoSOF->LinkSuspended	196	Covered	T5,T46,T70
LinkDisconnected->LinkPowered	151	Covered	T1,T2,T3
LinkPowered->LinkActiveNoSOF	157	Covered	T1,T2,T3
LinkPowered->LinkDisconnected	145	Covered	T7,T8,T47
LinkPowered->LinkPoweredSuspended	163	Covered	T1,T38,T11
LinkPowered->LinkResuming	161	Covered	T102,T103,T104
LinkPoweredSuspended->LinkActiveNoSOF	169	Not Covered
LinkPoweredSuspended->LinkDisconnected	145	Covered	T1,T38,T13
LinkPoweredSuspended->LinkPowered	172	Covered	T11,T104,T105
LinkResuming->LinkActiveNoSOF	186	Covered	T5,T46,T70
LinkResuming->LinkDisconnected	145	Not Covered
LinkSuspended->LinkActiveNoSOF	214	Not Covered
LinkSuspended->LinkDisconnected	145	Covered	T7,T8,T9
LinkSuspended->LinkResuming	216	Covered	T5,T46,T70

Summary for FSM :: link_rst_state_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: link_rst_state_q

---

states	Line No.	Covered	Tests
NoRst	262	Covered	T1,T2,T3
RstCnt	254	Covered	T1,T2,T3
RstPend	266	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
NoRst->RstCnt	254	Covered	T1,T2,T3
RstCnt->NoRst	262	Covered	T1,T2,T3
RstCnt->RstPend	266	Covered	T1,T2,T3
RstPend->NoRst	277	Covered	T1,T2,T3

Summary for FSM :: link_inac_state_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: link_inac_state_q

---

states	Line No.	Covered	Tests
Active	323	Covered	T1,T2,T3
InactCnt	316	Covered	T1,T2,T3
InactPend	326	Covered	T1,T38,T5

transitions	Line No.	Covered	Tests
Active->InactCnt	316	Covered	T1,T2,T3
InactCnt->Active	323	Covered	T1,T2,T3
InactCnt->InactPend	326	Covered	T1,T38,T5
InactPend->Active	337	Covered	T1,T38,T5

---

Branch Coverage for Module : usbdev_linkstate

	Line No.	Total	Covered	Percent
Branches		56	49	87.50
TERNARY	135	2	2	100.00
IF	144	22	18	81.82
IF	231	2	2	100.00
CASE	250	9	8	88.89
IF	292	2	2	100.00
CASE	311	9	7	77.78
IF	348	2	2	100.00
IF	367	4	4	100.00
IF	380	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_linkstate.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_linkstate.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	135	(see_pwr_sense) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	144	if (((!see_pwr_sense) || (!usb_pullup_en_i)))
-2-:	147	case (link_state_q)
-3-:	150	if ((see_pwr_sense & usb_pullup_en_i))
-4-:	156	if (ev_reset)
-5-:	158	if (resume_link_active_i)
-6-:	162	if (ev_bus_inactive)
-7-:	168	if (ev_reset)
-8-:	170	if (ev_bus_active)
-9-:	184	if ((rx_j_det_i | ev_reset))
-10-:	195	if (ev_bus_inactive)
-11-:	197	if (sof_detected_i)
-12-:	204	if (ev_bus_inactive)
-13-:	206	if (ev_reset)
-14-:	212	if (ev_reset)
-15-:	215	if (ev_bus_active)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	LinkDisconnected	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	LinkDisconnected	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
0	LinkPowered	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	LinkPowered	-	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T102,T103,T104
0	LinkPowered	-	0	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T38,T11
0	LinkPowered	-	0	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	LinkPoweredSuspended	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
0	LinkPoweredSuspended	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T11,T104,T105
0	LinkPoweredSuspended	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T38,T11
0	LinkResuming	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T46,T70
0	LinkResuming	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T5,T46,T70
0	LinkActiveNoSOF	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T5,T46,T70
0	LinkActiveNoSOF	-	-	-	-	-	-	-	0	1	-	-	-	-	Covered	T7,T21,T9
0	LinkActiveNoSOF	-	-	-	-	-	-	-	0	0	-	-	-	-	Covered	T1,T2,T3
0	LinkActive	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T7,T10,T101
0	LinkActive	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T21,T9,T12
0	LinkActive	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T7,T21,T9
0	LinkSuspended	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
0	LinkSuspended	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T5,T46,T70
0	LinkSuspended	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T5,T46,T70
0	default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	250	case (link_rst_state_q)
-2-:	253	if (see_se0)
-3-:	261	if ((!see_se0))
-4-:	264	if (us_tick_i)
-5-:	265	if ((link_rst_timer_q == RESET_TIMEOUT))
-6-:	276	if ((!see_se0))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
NoRst	1	-	-	-	-	Covered	T1,T2,T3
NoRst	0	-	-	-	-	Covered	T1,T2,T3
RstCnt	-	1	-	-	-	Covered	T1,T2,T3
RstCnt	-	0	1	1	-	Covered	T1,T2,T3
RstCnt	-	0	1	0	-	Covered	T1,T2,T3
RstCnt	-	0	0	-	-	Covered	T1,T2,T3
RstPend	-	-	-	-	1	Covered	T1,T2,T3
RstPend	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	292	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	311	case (link_inac_state_q)
-2-:	315	if (((!ev_bus_active) && monitor_inac))
-3-:	322	if ((ev_bus_active || (!monitor_inac)))
-4-:	324	if (us_tick_i)
-5-:	325	if ((link_inac_timer_q == SUSPEND_TIMEOUT))
-6-:	336	if ((ev_bus_active || (!monitor_inac)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
Active	1	-	-	-	-	Covered	T1,T2,T3
Active	0	-	-	-	-	Covered	T1,T2,T3
InactCnt	-	1	-	-	-	Covered	T1,T2,T3
InactCnt	-	0	1	1	-	Covered	T1,T38,T5
InactCnt	-	0	1	0	-	Covered	T1,T2,T3
InactCnt	-	0	0	-	-	Covered	T1,T2,T3
InactPend	-	-	-	-	1	Covered	T1,T38,T5
InactPend	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	348	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	367	if ((!rst_ni))
-2-:	370	if (((sof_detected_i || (!link_active_o)) || link_reset))
-3-:	372	if ((sof_missed_o && (!host_lost_o)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T5,T63
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	380	if ((!rst_ni))
-2-:	383	if ((((sof_missed_o || sof_detected_i) || (!link_active_o)) || link_reset))
-3-:	385	if (us_tick_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev_linkstate

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
LincInacStateValid_A	609017779	608731467	0	0
LinkRstStateValid_A	609017779	608731467	0	0
LinkStateValid_A	609017779	608731467	0	0

LincInacStateValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

LinkRstStateValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

LinkStateValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

Line Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate

	Line No.	Total	Covered	Percent
TOTAL		104	101	97.12
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
ALWAYS	139	34	31	91.18
ALWAYS	231	3	3	100.00
ALWAYS	245	18	18	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	292	5	5	100.00
ALWAYS	307	16	16	100.00
ALWAYS	348	5	5	100.00
CONT_ASSIGN	365	1	1	100.00
ALWAYS	367	6	6	100.00
CONT_ASSIGN	378	1	1	100.00
ALWAYS	380	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_linkstate.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_linkstate.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
92	1	1
93	1	1
94	1	1
96	1	1
99	1	1
105	1	1
133	1	1
135	1	1
139	1	1
140	1	1
144	1	1
145	1	1
147	1	1
150	1	1
151	1	1
			==> MISSING_ELSE
156	1	1
157	1	1
158	1	1
161	1	1
162	1	1
163	1	1
			MISSING_ELSE
168	1	1
169	0	1
170	1	1
171	1	1
172	1	1
			MISSING_ELSE
184	1	1
185	1	1
186	1	1
			MISSING_ELSE
195	1	1
196	1	1
197	1	1
198	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
212	1	1
213	0	1
214	0	1
215	1	1
216	1	1
			MISSING_ELSE
			Exclude Annotation: VC_COV_UNR
231	1	1
232	1	1
234	1	1
245	1	1
246	1	1
247	1	1
248	1	1
250	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
261	1	1
262	1	1
264	1	1
265	1	1
266	1	1
268	1	1
			MISSING_ELSE
276	1	1
277	1	1
278	1	1
			MISSING_ELSE
280	1	1
			Exclude Annotation: VC_COV_UNR
289	1	1
292	1	1
293	1	1
294	1	1
296	1	1
297	1	1
307	1	1
308	1	1
309	1	1
311	1	1
314	1	1
315	1	1
316	1	1
			MISSING_ELSE
322	1	1
323	1	1
324	1	1
325	1	1
326	1	1
327	1	1
329	1	1
			MISSING_ELSE
336	1	1
337	1	1
			==> MISSING_ELSE
			Exclude Annotation: VC_COV_UNR
348	1	1
349	1	1
350	1	1
352	1	1
353	1	1
365	1	1
367	1	1
368	1	1
370	1	1
371	1	1
372	1	1
373	1	1
			MISSING_ELSE
378	1	1
380	1	1
381	1	1
383	1	1
384	1	1
385	1	1
386	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate

	Total	Covered	Percent
Conditions	67	64	95.52
Logical	67	64	95.52
Non-Logical	0	0
Event	0	0

 LINE       92
 EXPRESSION (link_state_q == LinkDisconnected)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       94
 EXPRESSION ((link_state_q == LinkSuspended) || (link_state_q == LinkPoweredSuspended))
             ---------------1---------------    -------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T38,T11
1	0	Covered	T5,T46,T70

 LINE       94
 SUB-EXPRESSION (link_state_q == LinkSuspended)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T46,T70

 LINE       94
 SUB-EXPRESSION (link_state_q == LinkPoweredSuspended)
                -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T38,T11

 LINE       96
 EXPRESSION ((link_state_q == LinkActive) || (link_state_q == LinkActiveNoSOF))
             --------------1-------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T21,T9

 LINE       96
 SUB-EXPRESSION (link_state_q == LinkActive)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T21,T9

 LINE       96
 SUB-EXPRESSION (link_state_q == LinkActiveNoSOF)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       105
 EXPRESSION ((usb_dn_i == 1'b0) & (usb_dp_i == 1'b0) & (usb_oe_i == 1'b0))
             ---------1--------   ---------2--------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T39
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T3,T29
1	1	1	Covered	T1,T2,T3

 LINE       105
 SUB-EXPRESSION (usb_dn_i == 1'b0)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       105
 SUB-EXPRESSION (usb_dp_i == 1'b0)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       105
 SUB-EXPRESSION (usb_oe_i == 1'b0)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       135
 EXPRESSION (see_pwr_sense ? ((link_state_q == LinkPowered) | link_active_o) : 1'b0)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       135
 SUB-EXPRESSION ((link_state_q == LinkPowered) | link_active_o)
                 --------------1--------------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       135
 SUB-EXPRESSION (link_state_q == LinkPowered)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (((!see_pwr_sense)) || ((!usb_pullup_en_i)))
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T38
1	0	Covered	T3,T39,T29

 LINE       150
 EXPRESSION (see_pwr_sense & usb_pullup_en_i)
             ------1------   -------2-------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       184
 EXPRESSION (rx_j_det_i | ev_reset)
             -----1----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T46,T70
0	1	Not Covered
1	0	Covered	T5,T46,T70

 LINE       265
 EXPRESSION (link_rst_timer_q == RESET_TIMEOUT)
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       315
 EXPRESSION (((!ev_bus_active)) && monitor_inac)
             ---------1--------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T38,T5
1	1	Covered	T1,T2,T3

 LINE       322
 EXPRESSION (ev_bus_active || ((!monitor_inac)))
             ------1------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T38,T6
1	0	Covered	T1,T2,T3

 LINE       325
 EXPRESSION (link_inac_timer_q == SUSPEND_TIMEOUT)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T38,T5

 LINE       336
 EXPRESSION (ev_bus_active || ((!monitor_inac)))
             ------1------    --------2--------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T38,T5
1	0	Not Covered

 LINE       370
 EXPRESSION (sof_detected_i || ((!link_active_o)) || link_reset)
             -------1------    ---------2--------    -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T7,T21,T9

 LINE       372
 EXPRESSION (sof_missed_o && ((!host_lost_o)))
             ------1-----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T100
1	1	Covered	T4,T5,T63

 LINE       378
 EXPRESSION (missing_sof_timer == SOF_TIMEOUT)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T63

 LINE       383
 EXPRESSION (sof_missed_o || sof_detected_i || ((!link_active_o)) || link_reset)
             ------1-----    -------2------    ---------3--------    -----4----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	1	0	0	Covered	T7,T21,T9
1	0	0	0	Covered	T4,T5,T63

---

FSM Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate

Summary for FSM :: link_state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	19	16	84.21
Sequences	0	0

State, Transition and Sequence Details for FSM :: link_state_q

---

states	Line No.	Covered	Tests
LinkActive	198	Covered	T7,T21,T9
LinkActiveNoSOF	157	Covered	T1,T2,T3
LinkDisconnected	145	Covered	T1,T2,T3
LinkPowered	151	Covered	T1,T2,T3
LinkPoweredSuspended	163	Covered	T1,T38,T11
LinkResuming	161	Covered	T5,T46,T70
LinkSuspended	196	Covered	T5,T46,T70

transitions	Line No.	Covered	Tests
LinkActive->LinkActiveNoSOF	207	Covered	T21,T9,T12
LinkActive->LinkDisconnected	145	Covered	T67,T68,T69
LinkActive->LinkSuspended	205	Covered	T7,T10,T101
LinkActiveNoSOF->LinkActive	198	Covered	T7,T21,T9
LinkActiveNoSOF->LinkDisconnected	145	Covered	T1,T38,T31
LinkActiveNoSOF->LinkSuspended	196	Covered	T5,T46,T70
LinkDisconnected->LinkPowered	151	Covered	T1,T2,T3
LinkPowered->LinkActiveNoSOF	157	Covered	T1,T2,T3
LinkPowered->LinkDisconnected	145	Covered	T7,T8,T47
LinkPowered->LinkPoweredSuspended	163	Covered	T1,T38,T11
LinkPowered->LinkResuming	161	Covered	T102,T103,T104
LinkPoweredSuspended->LinkActiveNoSOF	169	Not Covered
LinkPoweredSuspended->LinkDisconnected	145	Covered	T1,T38,T13
LinkPoweredSuspended->LinkPowered	172	Covered	T11,T104,T105
LinkResuming->LinkActiveNoSOF	186	Covered	T5,T46,T70
LinkResuming->LinkDisconnected	145	Not Covered
LinkSuspended->LinkActiveNoSOF	214	Not Covered
LinkSuspended->LinkDisconnected	145	Covered	T7,T8,T9
LinkSuspended->LinkResuming	216	Covered	T5,T46,T70

Summary for FSM :: link_rst_state_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: link_rst_state_q

---

states	Line No.	Covered	Tests
NoRst	262	Covered	T1,T2,T3
RstCnt	254	Covered	T1,T2,T3
RstPend	266	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
NoRst->RstCnt	254	Covered	T1,T2,T3
RstCnt->NoRst	262	Covered	T1,T2,T3
RstCnt->RstPend	266	Covered	T1,T2,T3
RstPend->NoRst	277	Covered	T1,T2,T3

Summary for FSM :: link_inac_state_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: link_inac_state_q

---

states	Line No.	Covered	Tests
Active	323	Covered	T1,T2,T3
InactCnt	316	Covered	T1,T2,T3
InactPend	326	Covered	T1,T38,T5

transitions	Line No.	Covered	Tests
Active->InactCnt	316	Covered	T1,T2,T3
InactCnt->Active	323	Covered	T1,T2,T3
InactCnt->InactPend	326	Covered	T1,T38,T5
InactPend->Active	337	Covered	T1,T38,T5

---

Branch Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate

	Line No.	Total	Covered	Percent
Branches		52	49	94.23
TERNARY	135	2	2	100.00
IF	144	20	18	90.00
IF	231	2	2	100.00
CASE	250	8	8	100.00
IF	292	2	2	100.00
CASE	311	8	7	87.50
IF	348	2	2	100.00
IF	367	4	4	100.00
IF	380	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_linkstate.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_linkstate.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	135	(see_pwr_sense) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	144	if (((!see_pwr_sense) || (!usb_pullup_en_i)))
-2-:	147	case (link_state_q)
-3-:	150	if ((see_pwr_sense & usb_pullup_en_i))
-4-:	156	if (ev_reset)
-5-:	158	if (resume_link_active_i)
-6-:	162	if (ev_bus_inactive)
-7-:	168	if (ev_reset)
-8-:	170	if (ev_bus_active)
-9-:	184	if ((rx_j_det_i | ev_reset))
-10-:	195	if (ev_bus_inactive)
-11-:	197	if (sof_detected_i)
-12-:	204	if (ev_bus_inactive)
-13-:	206	if (ev_reset)
-14-:	212	if (ev_reset)
-15-:	215	if (ev_bus_active)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests	Exclude Annotation
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	LinkDisconnected	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	LinkDisconnected	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
0	LinkPowered	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	LinkPowered	-	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T102,T103,T104
0	LinkPowered	-	0	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T38,T11
0	LinkPowered	-	0	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	LinkPoweredSuspended	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
0	LinkPoweredSuspended	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T11,T104,T105
0	LinkPoweredSuspended	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T38,T11
0	LinkResuming	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T46,T70
0	LinkResuming	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T5,T46,T70
0	LinkActiveNoSOF	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T5,T46,T70
0	LinkActiveNoSOF	-	-	-	-	-	-	-	0	1	-	-	-	-	Covered	T7,T21,T9
0	LinkActiveNoSOF	-	-	-	-	-	-	-	0	0	-	-	-	-	Covered	T1,T2,T3
0	LinkActive	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T7,T10,T101
0	LinkActive	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T21,T9,T12
0	LinkActive	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T7,T21,T9
0	LinkSuspended	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
0	LinkSuspended	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T5,T46,T70
0	LinkSuspended	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T5,T46,T70
0	default	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	231	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	250	case (link_rst_state_q)
-2-:	253	if (see_se0)
-3-:	261	if ((!see_se0))
-4-:	264	if (us_tick_i)
-5-:	265	if ((link_rst_timer_q == RESET_TIMEOUT))
-6-:	276	if ((!see_se0))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests	Exclude Annotation
NoRst	1	-	-	-	-	Covered	T1,T2,T3
NoRst	0	-	-	-	-	Covered	T1,T2,T3
RstCnt	-	1	-	-	-	Covered	T1,T2,T3
RstCnt	-	0	1	1	-	Covered	T1,T2,T3
RstCnt	-	0	1	0	-	Covered	T1,T2,T3
RstCnt	-	0	0	-	-	Covered	T1,T2,T3
RstPend	-	-	-	-	1	Covered	T1,T2,T3
RstPend	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	292	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	311	case (link_inac_state_q)
-2-:	315	if (((!ev_bus_active) && monitor_inac))
-3-:	322	if ((ev_bus_active || (!monitor_inac)))
-4-:	324	if (us_tick_i)
-5-:	325	if ((link_inac_timer_q == SUSPEND_TIMEOUT))
-6-:	336	if ((ev_bus_active || (!monitor_inac)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests	Exclude Annotation
Active	1	-	-	-	-	Covered	T1,T2,T3
Active	0	-	-	-	-	Covered	T1,T2,T3
InactCnt	-	1	-	-	-	Covered	T1,T2,T3
InactCnt	-	0	1	1	-	Covered	T1,T38,T5
InactCnt	-	0	1	0	-	Covered	T1,T2,T3
InactCnt	-	0	0	-	-	Covered	T1,T2,T3
InactPend	-	-	-	-	1	Covered	T1,T38,T5
InactPend	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	348	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	367	if ((!rst_ni))
-2-:	370	if (((sof_detected_i || (!link_active_o)) || link_reset))
-3-:	372	if ((sof_missed_o && (!host_lost_o)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T5,T63
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	380	if ((!rst_ni))
-2-:	383	if ((((sof_missed_o || sof_detected_i) || (!link_active_o)) || link_reset))
-3-:	385	if (us_tick_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
LincInacStateValid_A	609017779	608731467	0	0
LinkRstStateValid_A	609017779	608731467	0	0
LinkStateValid_A	609017779	608731467	0	0

LincInacStateValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

LinkRstStateValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

LinkStateValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0