Unified Coverage Report :: Module Instance :: tb.dut.usbdev_avsetupfifo

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	96.77			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	96.77			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	98.59	88.57			96.00	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	98.59	88.57			96.00	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	98.59	88.57			96.00	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T91
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T39,T31,T32

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T96,T97
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T39,T31,T32

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T39,T31,T32
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T31,T32,T33

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T39,T31,T32
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	609017779	152891204	0	0
DepthKnown_A	609017779	608731467	0	0
RvalidKnown_A	609017779	608731467	0	0
WreadyKnown_A	609017779	608731467	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	609017779	152891204	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	152891204	0	0
T4	0	128103	0	0
T5	0	292282	0	0
T29	8225	0	0	0
T30	8394	0	0	0
T31	29599	1684	0	0
T32	24212	1699	0	0
T33	23305	1677	0	0
T34	12113	0	0	0
T35	29829	1706	0	0
T36	23483	1685	0	0
T39	23948	17267	0	0
T79	0	1823	0	0
T92	0	1716	0	0
T95	9170	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	152891204	0	0
T4	0	128103	0	0
T5	0	292282	0	0
T29	8225	0	0	0
T30	8394	0	0	0
T31	29599	1684	0	0
T32	24212	1699	0	0
T33	23305	1677	0	0
T34	12113	0	0	0
T35	29829	1706	0	0
T36	23483	1685	0	0
T39	23948	17267	0	0
T79	0	1823	0	0
T92	0	1716	0	0
T95	9170	0	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T91
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T39,T29

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T64,T65,T66
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T39,T29

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T2,T39,T29
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T30,T31

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T39,T29
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	609017779	301824411	0	0
DepthKnown_A	609017779	608731467	0	0
RvalidKnown_A	609017779	608731467	0	0
WreadyKnown_A	609017779	608731467	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	609017779	301824411	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	301824411	0	0
T2	8875	809	0	0
T3	6865	0	0	0
T29	8225	2491	0	0
T30	8394	700	0	0
T31	29599	1939	0	0
T32	24212	4826	0	0
T33	23305	3666	0	0
T34	12113	3511	0	0
T35	0	4456	0	0
T36	0	3717	0	0
T38	204883	0	0	0
T39	23948	15346	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	301824411	0	0
T2	8875	809	0	0
T3	6865	0	0	0
T29	8225	2491	0	0
T30	8394	700	0	0
T31	29599	1939	0	0
T32	24212	4826	0	0
T33	23305	3666	0	0
T34	12113	3511	0	0
T35	0	4456	0	0
T36	0	3717	0	0
T38	204883	0	0	0
T39	23948	15346	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T51,T52,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T30,T31

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T30,T31

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T2,T30,T31
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T30,T31,T32

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T30,T31
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T30,T31

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T30,T31
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	609017779	54977181	0	0
DepthKnown_A	609017779	608731467	0	0
RvalidKnown_A	609017779	608731467	0	0
WreadyKnown_A	609017779	608731467	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	609017779	54977181	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	54977181	0	0
T2	8875	1857	0	0
T3	6865	0	0	0
T4	0	2239	0	0
T29	8225	0	0	0
T30	8394	109	0	0
T31	29599	626	0	0
T32	24212	633	0	0
T33	23305	591	0	0
T34	12113	178	0	0
T35	0	623	0	0
T36	0	591	0	0
T37	0	113	0	0
T38	204883	0	0	0
T39	23948	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	54977181	0	0
T2	8875	1857	0	0
T3	6865	0	0	0
T4	0	2239	0	0
T29	8225	0	0	0
T30	8394	109	0	0
T31	29599	626	0	0
T32	24212	633	0	0
T33	23305	591	0	0
T34	12113	178	0	0
T35	0	623	0	0
T36	0	591	0	0
T37	0	113	0	0
T38	204883	0	0	0
T39	23948	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	610974013	19756862	0	0
DepthKnown_A	610974013	610643830	0	0
RvalidKnown_A	610974013	610643830	0	0
WreadyKnown_A	610974013	610643830	0	0
gen_passthru_fifo.paramCheckPass	3740	3740	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	19756862	0	0
T1	173756	16	0	0
T2	8875	16	0	0
T3	6865	9	0	0
T29	8225	10	0	0
T30	8394	15	0	0
T31	29599	101	0	0
T32	24212	115	0	0
T33	23305	112	0	0
T38	204883	16	0	0
T39	23948	60	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	610643830	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	610643830	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	610643830	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3740	3740	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	610974013	26804179	0	0
DepthKnown_A	610974013	610643830	0	0
RvalidKnown_A	610974013	610643830	0	0
WreadyKnown_A	610974013	610643830	0	0
gen_passthru_fifo.paramCheckPass	3740	3740	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	26804179	0	0
T1	173756	69	0	0
T2	8875	48	0	0
T3	6865	9	0	0
T29	8225	10	0	0
T30	8394	15	0	0
T31	29599	101	0	0
T32	24212	297	0	0
T33	23305	112	0	0
T38	204883	16	0	0
T39	23948	60	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	610643830	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	610643830	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	610643830	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3740	3740	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	610974013	954370	0	0
DepthKnown_A	610974013	610643830	0	0
RvalidKnown_A	610974013	610643830	0	0
WreadyKnown_A	610974013	610643830	0	0
gen_passthru_fifo.paramCheckPass	3740	3740	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	954370	0	0
T29	8225	0	0	0
T30	8394	0	0	0
T31	29599	45	0	0
T32	24212	59	0	0
T33	23305	53	0	0
T34	12113	23	0	0
T35	29829	53	0	0
T36	23483	56	0	0
T39	23948	6	0	0
T90	0	13	0	0
T92	0	39	0	0
T93	0	57	0	0
T95	9170	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	610643830	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	610643830	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	610643830	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3740	3740	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	610974013	1474551	0	0
DepthKnown_A	610974013	610643830	0	0
RvalidKnown_A	610974013	610643830	0	0
WreadyKnown_A	610974013	610643830	0	0
gen_passthru_fifo.paramCheckPass	3740	3740	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	1474551	0	0
T29	8225	0	0	0
T30	8394	0	0	0
T31	29599	45	0	0
T32	24212	167	0	0
T33	23305	53	0	0
T34	12113	23	0	0
T35	29829	231	0	0
T36	23483	56	0	0
T39	23948	6	0	0
T90	0	71	0	0
T92	0	39	0	0
T93	0	57	0	0
T95	9170	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	610643830	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	610643830	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	610643830	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3740	3740	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	610974013	18743938	0	0
DepthKnown_A	610974013	610643830	0	0
RvalidKnown_A	610974013	610643830	0	0
WreadyKnown_A	610974013	610643830	0	0
gen_passthru_fifo.paramCheckPass	3740	3740	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	18743938	0	0
T1	173756	16	0	0
T2	8875	16	0	0
T3	6865	9	0	0
T29	8225	10	0	0
T30	8394	15	0	0
T31	29599	56	0	0
T32	24212	56	0	0
T33	23305	59	0	0
T38	204883	16	0	0
T39	23948	54	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	610643830	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	610643830	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	610643830	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3740	3740	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	610974013	25329628	0	0
DepthKnown_A	610974013	610643830	0	0
RvalidKnown_A	610974013	610643830	0	0
WreadyKnown_A	610974013	610643830	0	0
gen_passthru_fifo.paramCheckPass	3740	3740	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	25329628	0	0
T1	173756	69	0	0
T2	8875	48	0	0
T3	6865	9	0	0
T29	8225	10	0	0
T30	8394	15	0	0
T31	29599	56	0	0
T32	24212	130	0	0
T33	23305	59	0	0
T38	204883	16	0	0
T39	23948	54	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	610643830	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	610643830	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610974013	610643830	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3740	3740	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T31,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T39,T31,T32

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T39,T31,T32

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T39,T31,T32
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T39,T31,T32

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T39,T31,T32
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T39,T31,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T39,T31,T32
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	609017779	1423522	0	0
DepthKnown_A	609017779	608731467	0	0
RvalidKnown_A	609017779	608731467	0	0
WreadyKnown_A	609017779	608731467	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	609017779	1423522	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	1423522	0	0
T29	8225	0	0	0
T30	8394	0	0	0
T31	29599	45	0	0
T32	24212	167	0	0
T33	23305	53	0	0
T34	12113	23	0	0
T35	29829	231	0	0
T36	23483	56	0	0
T39	23948	6	0	0
T90	0	71	0	0
T92	0	39	0	0
T93	0	57	0	0
T95	9170	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	1423522	0	0
T29	8225	0	0	0
T30	8394	0	0	0
T31	29599	45	0	0
T32	24212	167	0	0
T33	23305	53	0	0
T34	12113	23	0	0
T35	29829	231	0	0
T36	23483	56	0	0
T39	23948	6	0	0
T90	0	71	0	0
T92	0	39	0	0
T93	0	57	0	0
T95	9170	0	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T33
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T31,T32,T33

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T31,T32,T33

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T31,T32,T33

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	609017779	612030	0	0
DepthKnown_A	609017779	608731467	0	0
RvalidKnown_A	609017779	608731467	0	0
WreadyKnown_A	609017779	608731467	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	609017779	612030	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	612030	0	0
T4	133912	0	0	0
T31	29599	15	0	0
T32	24212	37	0	0
T33	23305	28	0	0
T34	12113	23	0	0
T35	29829	34	0	0
T36	23483	29	0	0
T37	9255	0	0	0
T90	0	13	0	0
T92	24436	20	0	0
T93	0	22	0	0
T94	0	36	0	0
T95	9170	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	612030	0	0
T4	133912	0	0	0
T31	29599	15	0	0
T32	24212	37	0	0
T33	23305	28	0	0
T34	12113	23	0	0
T35	29829	34	0	0
T36	23483	29	0	0
T37	9255	0	0	0
T90	0	13	0	0
T92	24436	20	0	0
T93	0	22	0	0
T94	0	36	0	0
T95	9170	0	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	18	18	100.00
Logical	18	18	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T32,T35,T90
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T31,T32,T33

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T31,T32,T33

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T31,T32,T33
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T31,T32,T33

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T31,T32,T33

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T31,T32,T33

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T32,T35,T90
1	0	Covered	T31,T32,T33
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	609017779	933502	0	0
DepthKnown_A	609017779	608731467	0	0
RvalidKnown_A	609017779	608731467	0	0
WreadyKnown_A	609017779	608731467	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	609017779	933502	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	933502	0	0
T4	133912	0	0	0
T31	29599	15	0	0
T32	24212	104	0	0
T33	23305	28	0	0
T34	12113	23	0	0
T35	29829	140	0	0
T36	23483	29	0	0
T37	9255	0	0	0
T90	0	71	0	0
T92	24436	20	0	0
T93	0	22	0	0
T94	0	36	0	0
T95	9170	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	608731467	0	0
T1	173756	173702	0	0
T2	8875	8780	0	0
T3	6865	6777	0	0
T29	8225	8130	0	0
T30	8394	8315	0	0
T31	29599	29542	0	0
T32	24212	24158	0	0
T33	23305	23198	0	0
T38	204883	204824	0	0
T39	23948	23850	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	609017779	933502	0	0
T4	133912	0	0	0
T31	29599	15	0	0
T32	24212	104	0	0
T33	23305	28	0	0
T34	12113	23	0	0
T35	29829	140	0	0
T36	23483	29	0	0
T37	9255	0	0	0
T90	0	71	0	0
T92	24436	20	0	0
T93	0	22	0	0
T94	0	36	0	0
T95	9170	0	0	0