Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9627244	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10255360

1

T1

7595

T2

135

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19220984	1			T1	15054		T2	90		T3	12
values[0x0]	330502	1			T1	104		T2	168		T3	4
values[0x1]	331118	1			T1	100		T2	172		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7651709	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

12230895

1

T1

9204

T2

184

T3

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	70131	1			T1	70		T27	17		T4	68
valid_sources[0x01]	58058	1			T1	64		T4	67		T29	1
valid_sources[0x02]	60200	1			T1	66		T4	57		T29	1
valid_sources[0x03]	87912	1			T1	56		T4	84		T83	60
valid_sources[0x04]	85477	1			T1	56		T4	81		T6	1
valid_sources[0x05]	112985	1			T1	53		T4	58		T22	43
valid_sources[0x06]	60191	1			T1	65		T4	52		T22	43
valid_sources[0x07]	80533	1			T1	54		T4	47		T6	3
valid_sources[0x08]	58084	1			T1	61		T4	60		T16	1
valid_sources[0x09]	65522	1			T1	67		T4	61		T82	13
valid_sources[0x0a]	60609	1			T1	49		T27	6		T4	67
valid_sources[0x0b]	75272	1			T1	79		T4	65		T6	6
valid_sources[0x0c]	168067	1			T1	59		T4	96		T29	2
valid_sources[0x0d]	57872	1			T1	57		T27	3		T4	72
valid_sources[0x0e]	58386	1			T1	54		T4	74		T22	110
valid_sources[0x0f]	61311	1			T1	55		T4	57		T22	55
valid_sources[0x10]	57614	1			T1	39		T4	102		T22	86
valid_sources[0x11]	58382	1			T1	41		T4	85		T22	72
valid_sources[0x12]	107128	1			T1	61		T4	89		T16	2
valid_sources[0x13]	60319	1			T1	66		T4	63		T29	1
valid_sources[0x14]	58042	1			T1	60		T4	87		T22	101
valid_sources[0x15]	66493	1			T1	47		T4	72		T6	2
valid_sources[0x16]	168295	1			T1	49		T4	65		T28	1
valid_sources[0x17]	102776	1			T1	65		T4	61		T6	2
valid_sources[0x18]	58255	1			T1	81		T4	68		T6	1
valid_sources[0x19]	146918	1			T1	64		T4	82		T6	7
valid_sources[0x1a]	58194	1			T1	66		T4	67		T22	88
valid_sources[0x1b]	58035	1			T1	55		T4	74		T29	1
valid_sources[0x1c]	78402	1			T1	63		T4	80		T83	124
valid_sources[0x1d]	57620	1			T1	61		T4	88		T29	3
valid_sources[0x1e]	57363	1			T1	55		T4	86		T29	1
valid_sources[0x1f]	58193	1			T1	48		T4	46		T22	67
valid_sources[0x20]	88349	1			T1	68		T4	68		T22	21
valid_sources[0x21]	74693	1			T1	53		T4	80		T28	1
valid_sources[0x22]	60196	1			T1	52		T4	67		T6	1
valid_sources[0x23]	67407	1			T1	62		T4	65		T82	10
valid_sources[0x24]	126622	1			T1	53		T4	43		T6	1
valid_sources[0x25]	58825	1			T1	56		T4	82		T18	3
valid_sources[0x26]	58261	1			T1	56		T4	79		T83	2
valid_sources[0x27]	59255	1			T1	65		T4	73		T22	39
valid_sources[0x28]	84179	1			T1	70		T4	98		T29	1
valid_sources[0x29]	58077	1			T1	43		T4	75		T29	4
valid_sources[0x2a]	57579	1			T1	52		T4	69		T29	1
valid_sources[0x2b]	57698	1			T1	48		T4	88		T22	57
valid_sources[0x2c]	60592	1			T1	57		T4	64		T22	34
valid_sources[0x2d]	58720	1			T1	56		T4	62		T20	1
valid_sources[0x2e]	92721	1			T1	66		T4	70		T22	91
valid_sources[0x2f]	104714	1			T1	48		T4	70		T29	2
valid_sources[0x30]	71599	1			T1	60		T4	84		T29	1
valid_sources[0x31]	74670	1			T1	86		T24	1		T4	62
valid_sources[0x32]	126822	1			T1	67		T4	79		T29	1
valid_sources[0x33]	302752	1			T1	58		T4	92		T22	108
valid_sources[0x34]	145061	1			T1	44		T4	80		T6	1
valid_sources[0x35]	58593	1			T1	46		T4	96		T22	30
valid_sources[0x36]	56549	1			T1	52		T4	86		T22	29
valid_sources[0x37]	58108	1			T1	72		T4	74		T28	1
valid_sources[0x38]	57608	1			T1	68		T3	20		T27	5
valid_sources[0x39]	197355	1			T1	51		T4	109		T31	6
valid_sources[0x3a]	59152	1			T1	42		T4	73		T6	2
valid_sources[0x3b]	59803	1			T1	65		T4	76		T6	1
valid_sources[0x3c]	81189	1			T1	44		T4	60		T22	93
valid_sources[0x3d]	58996	1			T1	74		T4	65		T6	1
valid_sources[0x3e]	57599	1			T1	74		T27	8		T4	94
valid_sources[0x3f]	57286	1			T1	47		T4	80		T22	72
valid_sources[0x40]	59047	1			T1	93		T4	65		T31	5
valid_sources[0x41]	75391	1			T1	55		T4	70		T29	2
valid_sources[0x42]	62484	1			T1	63		T2	78		T4	78
valid_sources[0x43]	59301	1			T1	67		T4	53		T22	163
valid_sources[0x44]	59709	1			T1	77		T4	71		T29	1
valid_sources[0x45]	59771	1			T1	35		T4	100		T22	15
valid_sources[0x46]	112608	1			T1	50		T4	51		T29	1
valid_sources[0x47]	58512	1			T1	72		T4	67		T22	39
valid_sources[0x48]	64894	1			T1	49		T4	64		T29	2
valid_sources[0x49]	64151	1			T1	66		T4	71		T29	7
valid_sources[0x4a]	59943	1			T1	57		T4	92		T29	2
valid_sources[0x4b]	59612	1			T1	66		T4	65		T22	87
valid_sources[0x4c]	233708	1			T1	64		T4	81		T37	3
valid_sources[0x4d]	102471	1			T1	73		T4	88		T6	1
valid_sources[0x4e]	56957	1			T1	52		T4	63		T30	5
valid_sources[0x4f]	57768	1			T1	64		T4	70		T29	1
valid_sources[0x50]	58653	1			T1	71		T4	48		T29	1
valid_sources[0x51]	170455	1			T1	39		T4	97		T29	1
valid_sources[0x52]	59108	1			T1	51		T4	63		T29	2
valid_sources[0x53]	142015	1			T1	56		T4	73		T22	50
valid_sources[0x54]	56504	1			T1	64		T4	56		T6	4
valid_sources[0x55]	59512	1			T1	60		T4	68		T22	62
valid_sources[0x56]	58757	1			T1	72		T4	57		T29	1
valid_sources[0x57]	60416	1			T1	95		T4	80		T20	1
valid_sources[0x58]	58576	1			T1	64		T4	90		T22	65
valid_sources[0x59]	83054	1			T1	95		T4	47		T29	1
valid_sources[0x5a]	75811	1			T1	47		T4	74		T29	1
valid_sources[0x5b]	57811	1			T1	62		T4	78		T32	10
valid_sources[0x5c]	58226	1			T1	58		T4	63		T22	78
valid_sources[0x5d]	59027	1			T1	47		T4	65		T6	1
valid_sources[0x5e]	59384	1			T1	70		T4	89		T22	94
valid_sources[0x5f]	70760	1			T1	65		T4	53		T6	1
valid_sources[0x60]	83837	1			T1	62		T4	82		T22	23
valid_sources[0x61]	110277	1			T1	55		T4	63		T22	87
valid_sources[0x62]	137482	1			T1	62		T4	64		T22	97
valid_sources[0x63]	59760	1			T1	62		T4	88		T29	2
valid_sources[0x64]	59324	1			T1	38		T27	8		T4	65
valid_sources[0x65]	58788	1			T1	76		T4	57		T6	1
valid_sources[0x66]	60036	1			T1	61		T4	68		T22	18
valid_sources[0x67]	57526	1			T1	44		T4	93		T19	1
valid_sources[0x68]	60113	1			T1	50		T4	75		T83	53
valid_sources[0x69]	91852	1			T1	69		T4	94		T22	59
valid_sources[0x6a]	58224	1			T1	40		T4	71		T22	71
valid_sources[0x6b]	67677	1			T1	64		T4	77		T29	1
valid_sources[0x6c]	58440	1			T1	51		T4	70		T29	1
valid_sources[0x6d]	58724	1			T1	60		T4	70		T6	1
valid_sources[0x6e]	58667	1			T1	68		T4	77		T22	112
valid_sources[0x6f]	58213	1			T1	45		T4	66		T22	56
valid_sources[0x70]	144341	1			T1	56		T4	69		T29	2
valid_sources[0x71]	58570	1			T1	65		T2	10		T4	77
valid_sources[0x72]	60264	1			T1	55		T4	83		T29	2
valid_sources[0x73]	105005	1			T1	82		T4	68		T22	36
valid_sources[0x74]	60586	1			T1	65		T4	52		T28	1
valid_sources[0x75]	108197	1			T1	58		T4	67		T22	21
valid_sources[0x76]	57490	1			T1	54		T2	20		T4	72
valid_sources[0x77]	57215	1			T1	71		T2	1		T4	56
valid_sources[0x78]	59548	1			T1	48		T4	92		T28	1
valid_sources[0x79]	58984	1			T1	42		T4	73		T29	1
valid_sources[0x7a]	58339	1			T1	50		T4	80		T29	2
valid_sources[0x7b]	58142	1			T1	84		T4	90		T37	3
valid_sources[0x7c]	123347	1			T1	55		T4	86		T22	119
valid_sources[0x7d]	127841	1			T1	65		T4	80		T29	1
valid_sources[0x7e]	59330	1			T1	66		T4	90		T83	129
valid_sources[0x7f]	57322	1			T1	55		T4	66		T22	29
valid_sources[0x80]	58754	1			T1	50		T4	84		T16	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9714259

1

T1

7461

T2

42

T3

7

values[0x0]

all_enables

biggest_size

279111

1

T1

75

T2

74

T3

2

values[0x1]

all_enables

biggest_size

261990

1

T1

59

T2

19

T3

1