Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

9639528

1

T1

7663

T2

295

T3

10

full_word

10256157

1

T1

7595

T2

135

T3

10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	19895405	1			T1	15258		T2	430		T3	20
auto[TlIntgErrCmd]	97	1			T204	5		T205	3		T247	5
auto[TlIntgErrData]	93	1			T204	1		T205	5		T247	2
auto[TlIntgErrBoth]	90	1			T204	4		T205	2		T247	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19222587

1

T1

15054

T2

90

T3

12

auto[1]

673098

1

T1

204

T2

340

T3

8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9508067	1			T1	7593		T2	48		T3	5
auto[TlIntgErrNone]	partial	auto[1]	131212	1			T1	70		T2	247		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	9714393	1			T1	7461		T2	42		T3	7
auto[TlIntgErrNone]	full_word	auto[1]	541733	1			T1	134		T2	93		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T204	3		T205	1		T247	2
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T204	2		T205	2		T247	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T251	1		T340	1		T337	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T247	1		T341	1		-	-
auto[TlIntgErrData]	partial	auto[0]	31	1			T205	2		T247	2		T251	2
auto[TlIntgErrData]	partial	auto[1]	50	1			T204	1		T205	3		T251	7
auto[TlIntgErrData]	full_word	auto[0]	8	1			T295	3		T342	2		T337	2
auto[TlIntgErrData]	full_word	auto[1]	4	1			T336	1		T343	1		T344	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T205	1		T247	2		T295	2
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T204	4		T205	1		T247	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T340	1		T339	1		T337	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T339	2		T337	1		T338	1