Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.83	97.53	92.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	590632846	10259	0	0
ep_in_enable_rd_A	590632846	3643	0	0
ep_out_enable_rd_A	590632846	2541	0	0
in_iso_rd_A	590632846	3467	0	0
intr_enable_rd_A	590632846	4725	0	0
out_iso_rd_A	590632846	3534	0	0
phy_config_rd_A	590632846	1712	0	0
phy_pins_drive_rd_A	590632846	2342	0	0
rxenable_setup_rd_A	590632846	3531	0	0
set_nak_out_rd_A	590632846	3244	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	10259	0	0
T204	17107	4	0	0
T205	15082	2	0	0
T206	9334	626	0	0
T237	4804	11	0	0
T238	3221	328	0	0
T247	26035	2	0	0
T248	3336	237	0	0
T258	4848	20	0	0
T259	4789	6	0	0
T260	5063	31	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	3643	0	0
T237	4804	6	0	0
T247	26035	185	0	0
T251	83909	656	0	0
T259	4789	37	0	0
T262	8171	33	0	0
T275	4871	4	0	0
T277	29371	98	0	0
T284	5768	28	0	0
T294	5223	3	0	0
T295	36414	678	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	2541	0	0
T237	4804	55	0	0
T247	26035	187	0	0
T251	83909	305	0	0
T259	4789	7	0	0
T262	8171	9	0	0
T275	4871	4	0	0
T277	29371	140	0	0
T294	5223	4	0	0
T295	36414	352	0	0
T296	5854	5	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	3467	0	0
T237	4804	65	0	0
T247	26035	413	0	0
T251	83909	508	0	0
T254	13582	10	0	0
T259	4789	63	0	0
T262	8171	3	0	0
T277	29371	132	0	0
T284	5768	3	0	0
T294	5223	2	0	0
T295	36414	374	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	4725	0	0
T237	4804	8	0	0
T247	26035	328	0	0
T251	83909	859	0	0
T259	4789	7	0	0
T284	5768	6	0	0
T294	5223	7	0	0
T297	3217	5	0	0
T298	3888	4	0	0
T299	4609	15	0	0
T300	4756	10	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	3534	0	0
T237	4804	54	0	0
T247	26035	129	0	0
T251	83909	465	0	0
T254	13582	7	0	0
T259	4789	12	0	0
T262	8171	36	0	0
T275	4871	6	0	0
T284	5768	35	0	0
T294	5223	10	0	0
T295	36414	444	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	1712	0	0
T237	4804	27	0	0
T247	26035	106	0	0
T251	83909	142	0	0
T259	4789	26	0	0
T262	8171	14	0	0
T277	29371	114	0	0
T284	5768	20	0	0
T294	5223	7	0	0
T295	36414	176	0	0
T296	5854	1	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	2342	0	0
T237	4804	37	0	0
T247	26035	205	0	0
T251	83909	300	0	0
T259	4789	50	0	0
T262	8171	36	0	0
T275	4871	1	0	0
T277	29371	151	0	0
T284	5768	24	0	0
T294	5223	4	0	0
T295	36414	272	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	3531	0	0
T206	9334	6	0	0
T237	4804	44	0	0
T247	26035	249	0	0
T251	83909	499	0	0
T259	4789	3	0	0
T262	8171	42	0	0
T275	4871	9	0	0
T284	5768	22	0	0
T294	5223	1	0	0
T295	36414	527	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	3244	0	0
T237	4804	42	0	0
T247	26035	316	0	0
T251	83909	511	0	0
T259	4789	11	0	0
T262	8171	43	0	0
T275	4871	5	0	0
T277	29371	114	0	0
T284	5768	1	0	0
T294	5223	6	0	0
T295	36414	532	0	0