Unified Coverage Report :: Module Instance :: tb.dut.usbdev_avsetupfifo

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.45	100.00	81.82			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.83	97.53	92.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	96.77			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.83	97.53	92.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.83	97.53	92.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	98.59	88.57			96.00	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	98.59	88.57			96.00	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	98.59	88.57			96.00	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	11	9	81.82
Logical	11	9	81.82
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T27

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T27

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T27
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T27,T4

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T27
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	588913596	133106811	0	0
DepthKnown_A	588913596	588625243	0	0
RvalidKnown_A	588913596	588625243	0	0
WreadyKnown_A	588913596	588625243	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	588913596	133106811	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	133106811	0	0
T1	169622	161564	0	0
T2	10584	2487	0	0
T3	9018	0	0	0
T4	376660	368123	0	0
T5	0	99505	0	0
T24	1659	0	0	0
T27	30198	1697	0	0
T28	7680	558	0	0
T29	23446	1701	0	0
T30	11455	0	0	0
T31	0	569	0	0
T32	7318	0	0	0
T82	0	15884	0	0
T83	0	2670	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	588625243	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	588625243	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	588625243	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	133106811	0	0
T1	169622	161564	0	0
T2	10584	2487	0	0
T3	9018	0	0	0
T4	376660	368123	0	0
T5	0	99505	0	0
T24	1659	0	0	0
T27	30198	1697	0	0
T28	7680	558	0	0
T29	23446	1701	0	0
T30	11455	0	0	0
T31	0	569	0	0
T32	7318	0	0	0
T82	0	15884	0	0
T83	0	2670	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T54,T55,T56
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T3,T27

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	588913596	282937461	0	0
DepthKnown_A	588913596	588625243	0	0
RvalidKnown_A	588913596	588625243	0	0
WreadyKnown_A	588913596	588625243	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	588913596	282937461	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	282937461	0	0
T1	169622	161489	0	0
T2	10584	3238	0	0
T3	9018	1169	0	0
T4	376660	368039	0	0
T24	1659	0	0	0
T27	30198	5875	0	0
T28	7680	0	0	0
T29	23446	2684	0	0
T30	11455	2105	0	0
T32	7318	1343	0	0
T82	0	5685	0	0
T83	0	2768	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	588625243	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	588625243	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	588625243	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	282937461	0	0
T1	169622	161489	0	0
T2	10584	3238	0	0
T3	9018	1169	0	0
T4	376660	368039	0	0
T24	1659	0	0	0
T27	30198	5875	0	0
T28	7680	0	0	0
T29	23446	2684	0	0
T30	11455	2105	0	0
T32	7318	1343	0	0
T82	0	5685	0	0
T83	0	2768	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T27

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T3,T27

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T27
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T3,T27

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T27
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T27
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	588913596	43846913	0	0
DepthKnown_A	588913596	588625243	0	0
RvalidKnown_A	588913596	588625243	0	0
WreadyKnown_A	588913596	588625243	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	588913596	43846913	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	43846913	0	0
T1	169622	1695	0	0
T2	10584	0	0	0
T3	9018	91	0	0
T4	376660	2264	0	0
T6	0	109	0	0
T17	0	10312	0	0
T24	1659	0	0	0
T27	30198	624	0	0
T28	7680	92	0	0
T29	23446	591	0	0
T30	11455	3283	0	0
T31	0	97	0	0
T32	7318	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	588625243	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	588625243	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	588625243	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	43846913	0	0
T1	169622	1695	0	0
T2	10584	0	0	0
T3	9018	91	0	0
T4	376660	2264	0	0
T6	0	109	0	0
T17	0	10312	0	0
T24	1659	0	0	0
T27	30198	624	0	0
T28	7680	92	0	0
T29	23446	591	0	0
T30	11455	3283	0	0
T31	0	97	0	0
T32	7318	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	590632846	20159585	0	0
DepthKnown_A	590632846	590306819	0	0
RvalidKnown_A	590632846	590306819	0	0
WreadyKnown_A	590632846	590306819	0	0
gen_passthru_fifo.paramCheckPass	3740	3740	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	20159585	0	0
T1	169622	15258	0	0
T2	10584	430	0	0
T3	9018	20	0	0
T4	376660	18459	0	0
T24	1659	5	0	0
T27	30198	142	0	0
T28	7680	14	0	0
T29	23446	103	0	0
T30	11455	16	0	0
T32	7318	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	590306819	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	590306819	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	590306819	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3740	3740	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T24	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	590632846	29034150	0	0
DepthKnown_A	590632846	590306819	0	0
RvalidKnown_A	590632846	590306819	0	0
WreadyKnown_A	590632846	590306819	0	0
gen_passthru_fifo.paramCheckPass	3740	3740	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	29034150	0	0
T1	169622	68550	0	0
T2	10584	1427	0	0
T3	9018	20	0	0
T4	376660	82716	0	0
T24	1659	5	0	0
T27	30198	142	0	0
T28	7680	14	0	0
T29	23446	103	0	0
T30	11455	16	0	0
T32	7318	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	590306819	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	590306819	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	590306819	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3740	3740	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T24	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	590632846	981512	0	0
DepthKnown_A	590632846	590306819	0	0
RvalidKnown_A	590632846	590306819	0	0
WreadyKnown_A	590632846	590306819	0	0
gen_passthru_fifo.paramCheckPass	3740	3740	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	981512	0	0
T1	169622	12	0	0
T2	10584	0	0	0
T3	9018	7	0	0
T4	376660	0	0	0
T23	0	55	0	0
T24	1659	0	0	0
T27	30198	83	0	0
T28	7680	2	0	0
T29	23446	42	0	0
T30	11455	0	0	0
T31	0	2	0	0
T32	7318	0	0	0
T81	0	15	0	0
T82	0	14	0	0
T84	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	590306819	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	590306819	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	590306819	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3740	3740	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T24	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	590632846	1908977	0	0
DepthKnown_A	590632846	590306819	0	0
RvalidKnown_A	590632846	590306819	0	0
WreadyKnown_A	590632846	590306819	0	0
gen_passthru_fifo.paramCheckPass	3740	3740	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	1908977	0	0
T1	169622	48	0	0
T2	10584	0	0	0
T3	9018	7	0	0
T4	376660	0	0	0
T23	0	55	0	0
T24	1659	0	0	0
T27	30198	83	0	0
T28	7680	2	0	0
T29	23446	42	0	0
T30	11455	0	0	0
T31	0	8	0	0
T32	7318	0	0	0
T81	0	36	0	0
T82	0	14	0	0
T84	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	590306819	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	590306819	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	590306819	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3740	3740	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T24	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	590632846	19115597	0	0
DepthKnown_A	590632846	590306819	0	0
RvalidKnown_A	590632846	590306819	0	0
WreadyKnown_A	590632846	590306819	0	0
gen_passthru_fifo.paramCheckPass	3740	3740	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	19115597	0	0
T1	169622	15246	0	0
T2	10584	430	0	0
T3	9018	13	0	0
T4	376660	18459	0	0
T24	1659	5	0	0
T27	30198	59	0	0
T28	7680	12	0	0
T29	23446	61	0	0
T30	11455	16	0	0
T32	7318	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	590306819	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	590306819	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	590306819	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3740	3740	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T24	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	590632846	27125173	0	0
DepthKnown_A	590632846	590306819	0	0
RvalidKnown_A	590632846	590306819	0	0
WreadyKnown_A	590632846	590306819	0	0
gen_passthru_fifo.paramCheckPass	3740	3740	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	27125173	0	0
T1	169622	68502	0	0
T2	10584	1427	0	0
T3	9018	13	0	0
T4	376660	82716	0	0
T24	1659	5	0	0
T27	30198	59	0	0
T28	7680	12	0	0
T29	23446	61	0	0
T30	11455	16	0	0
T32	7318	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	590306819	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	590306819	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590632846	590306819	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3740	3740	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T24	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T27

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T3,T27

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T1,T27,T28
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T3,T27

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T27
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T27
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	588913596	1846572	0	0
DepthKnown_A	588913596	588625243	0	0
RvalidKnown_A	588913596	588625243	0	0
WreadyKnown_A	588913596	588625243	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	588913596	1846572	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	1846572	0	0
T1	169622	48	0	0
T2	10584	0	0	0
T3	9018	7	0	0
T4	376660	0	0	0
T23	0	55	0	0
T24	1659	0	0	0
T27	30198	83	0	0
T28	7680	2	0	0
T29	23446	42	0	0
T30	11455	0	0	0
T31	0	8	0	0
T32	7318	0	0	0
T81	0	36	0	0
T82	0	14	0	0
T84	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	588625243	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	588625243	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	588625243	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	1846572	0	0
T1	169622	48	0	0
T2	10584	0	0	0
T3	9018	7	0	0
T4	376660	0	0	0
T23	0	55	0	0
T24	1659	0	0	0
T27	30198	83	0	0
T28	7680	2	0	0
T29	23446	42	0	0
T30	11455	0	0	0
T31	0	8	0	0
T32	7318	0	0	0
T81	0	36	0	0
T82	0	14	0	0
T84	0	8	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T27

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T3,T27

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T3,T27

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T27
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T27
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	588913596	625838	0	0
DepthKnown_A	588913596	588625243	0	0
RvalidKnown_A	588913596	588625243	0	0
WreadyKnown_A	588913596	588625243	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	588913596	625838	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	625838	0	0
T1	169622	6	0	0
T2	10584	0	0	0
T3	9018	7	0	0
T4	376660	0	0	0
T23	0	29	0	0
T24	1659	0	0	0
T27	30198	46	0	0
T28	7680	2	0	0
T29	23446	20	0	0
T30	11455	0	0	0
T31	0	2	0	0
T32	7318	0	0	0
T81	0	15	0	0
T84	0	8	0	0
T85	0	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	588625243	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	588625243	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	588625243	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	625838	0	0
T1	169622	6	0	0
T2	10584	0	0	0
T3	9018	7	0	0
T4	376660	0	0	0
T23	0	29	0	0
T24	1659	0	0	0
T27	30198	46	0	0
T28	7680	2	0	0
T29	23446	20	0	0
T30	11455	0	0	0
T31	0	2	0	0
T32	7318	0	0	0
T81	0	15	0	0
T84	0	8	0	0
T85	0	18	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	18	18	100.00
Logical	18	18	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T31,T81
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T27

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T3,T27

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T1,T27,T28
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T3,T27

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T27

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T27

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T31,T81
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T27
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T27
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	588913596	1270848	0	0
DepthKnown_A	588913596	588625243	0	0
RvalidKnown_A	588913596	588625243	0	0
WreadyKnown_A	588913596	588625243	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	588913596	1270848	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	1270848	0	0
T1	169622	26	0	0
T2	10584	0	0	0
T3	9018	7	0	0
T4	376660	0	0	0
T23	0	29	0	0
T24	1659	0	0	0
T27	30198	46	0	0
T28	7680	2	0	0
T29	23446	20	0	0
T30	11455	0	0	0
T31	0	8	0	0
T32	7318	0	0	0
T81	0	36	0	0
T84	0	8	0	0
T85	0	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	588625243	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	588625243	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	588625243	0	0
T1	169622	169539	0	0
T2	10584	10529	0	0
T3	9018	8947	0	0
T4	376660	376602	0	0
T24	1659	1604	0	0
T27	30198	30058	0	0
T28	7680	7599	0	0
T29	23446	23267	0	0
T30	11455	11364	0	0
T32	7318	7223	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	588913596	1270848	0	0
T1	169622	26	0	0
T2	10584	0	0	0
T3	9018	7	0	0
T4	376660	0	0	0
T23	0	29	0	0
T24	1659	0	0	0
T27	30198	46	0	0
T28	7680	2	0	0
T29	23446	20	0	0
T30	11455	0	0	0
T31	0	8	0	0
T32	7318	0	0	0
T81	0	36	0	0
T84	0	8	0	0
T85	0	18	0	0