Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9603602	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10162721

1

T1

4

T2

7

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19129267	1			T1	3		T2	2		T3	3
values[0x0]	317284	1			T1	2		T2	4		T3	3
values[0x1]	319772	1			T2	4		T3	6		T27	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7633250	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

12133073

1

T1

4

T2

9

T3

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	75645	1			T4	82		T30	7		T5	268
valid_sources[0x01]	62999	1			T4	89		T30	6		T31	1
valid_sources[0x02]	67057	1			T4	73		T30	16		T31	1
valid_sources[0x03]	85380	1			T4	75		T30	4		T33	3
valid_sources[0x04]	60992	1			T4	85		T30	8		T5	228
valid_sources[0x05]	60404	1			T4	81		T30	16		T91	1
valid_sources[0x06]	87905	1			T4	94		T30	8		T34	8
valid_sources[0x07]	60618	1			T4	86		T30	28		T31	2
valid_sources[0x08]	80178	1			T4	93		T28	3		T30	17
valid_sources[0x09]	60143	1			T4	85		T31	2		T36	1
valid_sources[0x0a]	59461	1			T4	88		T30	10		T31	1
valid_sources[0x0b]	61431	1			T4	93		T30	5		T32	1
valid_sources[0x0c]	60522	1			T4	77		T30	18		T36	1
valid_sources[0x0d]	59875	1			T4	73		T30	8		T36	2
valid_sources[0x0e]	64922	1			T4	97		T30	7		T32	1
valid_sources[0x0f]	60191	1			T4	85		T30	38		T31	3
valid_sources[0x10]	60300	1			T4	78		T30	27		T91	1
valid_sources[0x11]	101764	1			T4	87		T30	5		T5	316
valid_sources[0x12]	59943	1			T4	81		T30	18		T5	315
valid_sources[0x13]	60667	1			T4	73		T30	7		T91	1
valid_sources[0x14]	60544	1			T4	92		T30	4		T31	2
valid_sources[0x15]	106303	1			T4	83		T30	22		T32	1
valid_sources[0x16]	90258	1			T4	86		T30	12		T36	1
valid_sources[0x17]	59518	1			T4	99		T30	8		T35	1
valid_sources[0x18]	60320	1			T27	1		T4	80		T37	11
valid_sources[0x19]	61336	1			T4	76		T30	3		T32	1
valid_sources[0x1a]	106112	1			T4	78		T30	15		T31	1
valid_sources[0x1b]	76097	1			T4	83		T30	3		T5	321
valid_sources[0x1c]	128224	1			T4	94		T30	16		T31	1
valid_sources[0x1d]	71280	1			T4	80		T30	8		T35	4
valid_sources[0x1e]	114858	1			T4	68		T30	14		T5	268
valid_sources[0x1f]	96819	1			T4	72		T30	9		T31	1
valid_sources[0x20]	59241	1			T4	104		T30	5		T5	276
valid_sources[0x21]	61541	1			T4	93		T30	2		T5	292
valid_sources[0x22]	59652	1			T4	87		T30	5		T31	1
valid_sources[0x23]	60507	1			T4	64		T30	20		T91	2
valid_sources[0x24]	60320	1			T4	85		T30	15		T91	1
valid_sources[0x25]	60906	1			T4	82		T30	17		T35	4
valid_sources[0x26]	120371	1			T4	82		T30	15		T5	259
valid_sources[0x27]	60972	1			T4	67		T30	1		T5	254
valid_sources[0x28]	97095	1			T4	78		T30	7		T35	1
valid_sources[0x29]	60544	1			T4	57		T30	11		T19	1
valid_sources[0x2a]	60321	1			T4	83		T30	9		T36	7
valid_sources[0x2b]	79183	1			T4	89		T30	7		T35	2
valid_sources[0x2c]	102967	1			T4	87		T30	8		T36	3
valid_sources[0x2d]	68479	1			T4	92		T30	18		T35	1
valid_sources[0x2e]	173015	1			T4	80		T30	1		T5	235
valid_sources[0x2f]	63536	1			T4	83		T30	15		T91	1
valid_sources[0x30]	117680	1			T4	83		T30	4		T35	1
valid_sources[0x31]	65814	1			T4	70		T30	9		T36	2
valid_sources[0x32]	61314	1			T4	100		T30	6		T91	1
valid_sources[0x33]	59843	1			T4	75		T30	15		T35	1
valid_sources[0x34]	60655	1			T4	102		T28	3		T30	12
valid_sources[0x35]	77345	1			T4	106		T30	7		T36	7
valid_sources[0x36]	60548	1			T4	59		T30	6		T36	2
valid_sources[0x37]	60046	1			T4	66		T30	1		T59	6
valid_sources[0x38]	73983	1			T4	72		T30	7		T31	1
valid_sources[0x39]	148091	1			T4	78		T30	2		T5	271
valid_sources[0x3a]	74313	1			T4	87		T30	16		T36	3
valid_sources[0x3b]	61309	1			T4	96		T30	32		T36	3
valid_sources[0x3c]	59618	1			T4	69		T30	4		T5	341
valid_sources[0x3d]	59921	1			T2	4		T4	93		T30	3
valid_sources[0x3e]	61426	1			T4	84		T30	17		T91	1
valid_sources[0x3f]	90314	1			T4	85		T30	5		T36	2
valid_sources[0x40]	60745	1			T4	83		T30	7		T5	235
valid_sources[0x41]	59867	1			T4	68		T30	10		T31	1
valid_sources[0x42]	59955	1			T4	86		T30	5		T5	283
valid_sources[0x43]	131332	1			T4	77		T30	13		T5	287
valid_sources[0x44]	59859	1			T4	74		T30	6		T5	293
valid_sources[0x45]	61636	1			T4	70		T30	7		T36	1
valid_sources[0x46]	59764	1			T4	86		T30	2		T5	264
valid_sources[0x47]	60086	1			T4	84		T30	13		T36	1
valid_sources[0x48]	151578	1			T4	81		T30	23		T36	1
valid_sources[0x49]	74062	1			T4	88		T30	21		T36	1
valid_sources[0x4a]	59850	1			T27	1		T4	68		T30	10
valid_sources[0x4b]	60634	1			T4	101		T30	3		T36	1
valid_sources[0x4c]	114575	1			T4	80		T30	17		T36	8
valid_sources[0x4d]	60203	1			T4	63		T30	12		T5	259
valid_sources[0x4e]	87995	1			T4	88		T30	22		T5	315
valid_sources[0x4f]	61259	1			T4	89		T30	11		T5	270
valid_sources[0x50]	59215	1			T4	84		T30	1		T31	3
valid_sources[0x51]	60991	1			T4	115		T30	4		T35	1
valid_sources[0x52]	59583	1			T4	51		T30	7		T59	1
valid_sources[0x53]	170112	1			T4	70		T30	11		T91	1
valid_sources[0x54]	61168	1			T4	69		T28	5		T30	8
valid_sources[0x55]	108567	1			T4	92		T30	15		T34	6
valid_sources[0x56]	60963	1			T27	1		T4	90		T30	21
valid_sources[0x57]	94448	1			T4	82		T30	15		T36	2
valid_sources[0x58]	61106	1			T4	72		T30	14		T35	2
valid_sources[0x59]	60551	1			T4	84		T30	15		T5	292
valid_sources[0x5a]	73589	1			T4	103		T30	30		T35	1
valid_sources[0x5b]	60443	1			T4	79		T28	1		T30	2
valid_sources[0x5c]	59465	1			T4	88		T30	21		T35	2
valid_sources[0x5d]	64247	1			T4	90		T30	5		T32	1
valid_sources[0x5e]	62817	1			T4	91		T30	14		T35	1
valid_sources[0x5f]	77174	1			T4	81		T30	18		T32	1
valid_sources[0x60]	60628	1			T4	67		T30	3		T5	280
valid_sources[0x61]	60592	1			T4	74		T30	2		T32	1
valid_sources[0x62]	307793	1			T4	86		T30	10		T35	1
valid_sources[0x63]	111809	1			T4	80		T30	16		T36	1
valid_sources[0x64]	60875	1			T4	77		T30	17		T5	260
valid_sources[0x65]	59375	1			T4	93		T30	19		T5	261
valid_sources[0x66]	74941	1			T4	74		T30	6		T5	228
valid_sources[0x67]	64242	1			T4	96		T30	13		T36	3
valid_sources[0x68]	60009	1			T4	92		T30	14		T91	1
valid_sources[0x69]	59479	1			T4	84		T30	5		T36	1
valid_sources[0x6a]	61018	1			T4	86		T30	19		T31	2
valid_sources[0x6b]	104599	1			T4	88		T30	20		T5	291
valid_sources[0x6c]	59756	1			T4	95		T30	15		T36	5
valid_sources[0x6d]	58911	1			T4	81		T30	4		T35	4
valid_sources[0x6e]	60274	1			T4	74		T30	8		T34	7
valid_sources[0x6f]	60447	1			T4	80		T30	4		T5	260
valid_sources[0x70]	61000	1			T4	89		T30	6		T5	259
valid_sources[0x71]	186070	1			T4	75		T30	25		T35	2
valid_sources[0x72]	128258	1			T4	63		T30	8		T5	334
valid_sources[0x73]	59279	1			T4	85		T30	5		T36	3
valid_sources[0x74]	107634	1			T4	74		T30	17		T5	272
valid_sources[0x75]	168902	1			T4	95		T29	13		T30	31
valid_sources[0x76]	59289	1			T4	74		T30	16		T5	258
valid_sources[0x77]	61506	1			T4	78		T30	6		T36	5
valid_sources[0x78]	141866	1			T4	87		T30	8		T36	3
valid_sources[0x79]	59190	1			T4	73		T30	23		T36	2
valid_sources[0x7a]	83912	1			T4	70		T30	23		T32	1
valid_sources[0x7b]	71482	1			T4	68		T30	8		T35	1
valid_sources[0x7c]	61231	1			T4	88		T30	5		T91	1
valid_sources[0x7d]	58995	1			T4	79		T28	1		T30	6
valid_sources[0x7e]	60269	1			T4	85		T30	2		T31	2
valid_sources[0x7f]	99390	1			T4	74		T30	6		T91	1
valid_sources[0x80]	144685	1			T4	75		T30	19		T31	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9645046

1

T1

2

T2

1

T3

1

values[0x0]

all_enables

biggest_size

266698

1

T1

2

T2

4

T3

1

values[0x1]

all_enables

biggest_size

250977

1

T2

2

T3

3

T27

4