Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

9617854

1

T1

1

T2

3

T3

7

full_word

10163718

1

T1

4

T2

7

T3

5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	19781282	1			T1	5		T2	10		T3	12
auto[TlIntgErrCmd]	102	1			T278	9		T284	7		T285	2
auto[TlIntgErrData]	99	1			T278	6		T284	9		T285	6
auto[TlIntgErrBoth]	89	1			T278	5		T284	4		T285	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19131116

1

T1

3

T2

2

T3

3

auto[1]

650456

1

T1

2

T2

8

T3

9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9485764	1			T1	1		T2	1		T3	2
auto[TlIntgErrNone]	partial	auto[1]	131826	1			T2	2		T3	5		T27	3
auto[TlIntgErrNone]	full_word	auto[0]	9645225	1			T1	2		T2	1		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	518467	1			T1	2		T2	6		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T278	3		T284	2		T285	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T278	5		T284	5		T519	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T278	1		T305	1		T523	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T343	1		T524	1		T525	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T278	2		T284	3		T285	4
auto[TlIntgErrData]	partial	auto[1]	43	1			T278	4		T284	5		T285	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T284	1		T520	1		T522	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T285	1		T305	1		T519	1
auto[TlIntgErrBoth]	partial	auto[0]	29	1			T278	2		T284	2		T285	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T278	3		T284	2		T285	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T343	1		T526	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T519	1		T343	1		T521	1