Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	589327825	11244	0	0
ep_in_enable_rd_A	589327825	2600	0	0
ep_out_enable_rd_A	589327825	2569	0	0
in_iso_rd_A	589327825	2446	0	0
intr_enable_rd_A	589327825	3628	0	0
out_iso_rd_A	589327825	2571	0	0
phy_config_rd_A	589327825	1827	0	0
phy_pins_drive_rd_A	589327825	2172	0	0
rxenable_setup_rd_A	589327825	2758	0	0
set_nak_out_rd_A	589327825	2386	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	11244	0	0
T242	3660	8	0	0
T243	7114	316	0	0
T244	4915	234	0	0
T277	4276	6	0	0
T278	98611	4	0	0
T279	4125	438	0	0
T284	36551	3	0	0
T285	16757	3	0	0
T291	3947	27	0	0
T299	8865	18	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	2600	0	0
T284	36551	257	0	0
T304	5123	66	0	0
T306	5454	49	0	0
T325	3825	7	0	0
T330	37086	184	0	0
T336	5862	7	0	0
T342	43943	229	0	0
T343	62515	259	0	0
T344	7615	29	0	0
T345	5074	38	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	2569	0	0
T284	36551	388	0	0
T301	2237	9	0	0
T304	5123	6	0	0
T306	5454	7	0	0
T325	3825	40	0	0
T330	37086	196	0	0
T342	43943	205	0	0
T343	62515	263	0	0
T344	7615	24	0	0
T345	5074	39	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	2446	0	0
T243	7114	1	0	0
T284	36551	173	0	0
T304	5123	3	0	0
T306	5454	6	0	0
T325	3825	40	0	0
T336	5862	15	0	0
T342	43943	230	0	0
T343	62515	258	0	0
T344	7615	43	0	0
T345	5074	29	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	3628	0	0
T249	4495	21	0	0
T251	1904	8	0	0
T284	36551	662	0	0
T304	5123	11	0	0
T306	5454	60	0	0
T325	3825	110	0	0
T336	5862	36	0	0
T342	43943	250	0	0
T346	2236	17	0	0
T347	1859	13	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	2571	0	0
T284	36551	374	0	0
T304	5123	9	0	0
T306	5454	3	0	0
T325	3825	32	0	0
T330	37086	217	0	0
T336	5862	26	0	0
T342	43943	220	0	0
T343	62515	245	0	0
T344	7615	39	0	0
T345	5074	17	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	1827	0	0
T284	36551	118	0	0
T292	14924	4	0	0
T301	2237	6	0	0
T304	5123	10	0	0
T306	5454	22	0	0
T325	3825	21	0	0
T336	5862	10	0	0
T342	43943	195	0	0
T343	62515	178	0	0
T344	7615	8	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	2172	0	0
T284	36551	217	0	0
T292	14924	5	0	0
T301	2237	6	0	0
T304	5123	41	0	0
T306	5454	8	0	0
T325	3825	21	0	0
T336	5862	46	0	0
T342	43943	207	0	0
T343	62515	270	0	0
T344	7615	44	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	2758	0	0
T284	36551	193	0	0
T301	2237	41	0	0
T304	5123	7	0	0
T306	5454	46	0	0
T325	3825	59	0	0
T336	5862	37	0	0
T342	43943	239	0	0
T343	62515	372	0	0
T344	7615	25	0	0
T345	5074	7	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	2386	0	0
T284	36551	319	0	0
T301	2237	4	0	0
T304	5123	5	0	0
T306	5454	46	0	0
T325	3825	59	0	0
T336	5862	25	0	0
T342	43943	246	0	0
T343	62515	324	0	0
T344	7615	19	0	0
T345	5074	29	0	0