Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_filter
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.usbdev_impl.u_usbdev_linkstate.filter_se0 100.00 100.00 100.00 100.00
tb.dut.usbdev_impl.u_usbdev_linkstate.filter_pwr_sense 100.00 100.00 100.00 100.00


Module Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_se0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.33 97.12 95.52 96.00 98.00 100.00 u_usbdev_linkstate


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_pwr_sense

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.33 97.12 95.52 96.00 98.00 100.00 u_usbdev_linkstate


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_filter
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN4411100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
48 1 1
49 1 1
50 1 1
51 1 1
MISSING_ELSE
55 1 1
56 1 1
59 1 1
60 1 1
62 1 1
66 1 1
70 1 1

Cond Coverage for Module : prim_filter
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3
Branch Coverage for Module : prim_filter
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 70 1 1 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	70	(enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable 



	LineNo.	Expression
-1-:	48	if ((!rst_ni))
-2-:	50	if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	59	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_se0
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN4411100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
48 1 1
49 1 1
50 1 1
51 1 1
MISSING_ELSE
55 1 1
56 1 1
59 1 1
60 1 1
62 1 1
66 1 1
70 1 1

Cond Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_se0
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T27 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T27 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_se0
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 70 1 1 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	70	(enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable 



	LineNo.	Expression
-1-:	48	if ((!rst_ni))
-2-:	50	if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	59	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_pwr_sense
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN4411100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
48 1 1
49 1 1
50 1 1
51 1 1
MISSING_ELSE
55 1 1
56 1 1
59 1 1
60 1 1
62 1 1
66 1 1
70 1 1

Cond Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_pwr_sense
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT2,T3,T27
01CoveredT2,T3,T27
10CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T27 

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_pwr_sense
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 70 1 1 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	70	(enable_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable 



	LineNo.	Expression
-1-:	48	if ((!rst_ni))
-2-:	50	if (update_stored_value)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T2,T3,T27 



	LineNo.	Expression
-1-:	59	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%