Unified Coverage Report :: Module Instance :: tb.dut.usbdev_avsetupfifo

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	96.77			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	96.77			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	98.59	88.57			96.00	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	98.59	88.57			96.00	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	98.59	88.57			96.00	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T4,T31,T91

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T93
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T31,T91

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T4,T31,T91
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T31,T35,T20

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T31,T91
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	587461143	130839063	0	0
DepthKnown_A	587461143	587174254	0	0
RvalidKnown_A	587461143	587174254	0	0
WreadyKnown_A	587461143	587174254	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	587461143	130839063	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	130839063	0	0
T4	156637	150495	0	0
T5	0	142644	0	0
T20	0	6106	0	0
T25	2280	0	0	0
T28	10274	0	0	0
T29	8078	0	0	0
T30	293879	0	0	0
T31	12474	582	0	0
T32	10209	0	0	0
T33	9482	0	0	0
T35	0	1677	0	0
T37	7513	0	0	0
T46	0	1694	0	0
T76	0	1723	0	0
T79	0	1705	0	0
T91	17900	1973	0	0
T92	0	1344	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	587174254	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	587174254	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	587174254	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	130839063	0	0
T4	156637	150495	0	0
T5	0	142644	0	0
T20	0	6106	0	0
T25	2280	0	0	0
T28	10274	0	0	0
T29	8078	0	0	0
T30	293879	0	0	0
T31	12474	582	0	0
T32	10209	0	0	0
T33	9482	0	0	0
T35	0	1677	0	0
T37	7513	0	0	0
T46	0	1694	0	0
T76	0	1723	0	0
T79	0	1705	0	0
T91	17900	1973	0	0
T92	0	1344	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T94
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T27

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T63,T64,T65
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T3,T27

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T27
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T27,T4

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T27
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	587461143	276616436	0	0
DepthKnown_A	587461143	587174254	0	0
RvalidKnown_A	587461143	587174254	0	0
WreadyKnown_A	587461143	587174254	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	587461143	276616436	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	276616436	0	0
T2	7618	1051	0	0
T3	11814	2380	0	0
T4	156637	150431	0	0
T25	2280	0	0	0
T27	8551	497	0	0
T28	10274	3454	0	0
T29	8078	438	0	0
T30	293879	186434	0	0
T31	12474	2147	0	0
T32	0	2381	0	0
T37	7513	0	0	0
T91	0	7398	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	587174254	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	587174254	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	587174254	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	276616436	0	0
T2	7618	1051	0	0
T3	11814	2380	0	0
T4	156637	150431	0	0
T25	2280	0	0	0
T27	8551	497	0	0
T28	10274	3454	0	0
T29	8078	438	0	0
T30	293879	186434	0	0
T31	12474	2147	0	0
T32	0	2381	0	0
T37	7513	0	0	0
T91	0	7398	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T50,T51
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T3,T27,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T27,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T3,T27,T4
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T28,T29

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T27,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T27,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T27,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	587461143	43837461	0	0
DepthKnown_A	587461143	587174254	0	0
RvalidKnown_A	587461143	587174254	0	0
WreadyKnown_A	587461143	587174254	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	587461143	43837461	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	43837461	0	0
T3	11814	3371	0	0
T4	156637	860	0	0
T25	2280	0	0	0
T27	8551	1502	0	0
T28	10274	93	0	0
T29	8078	103	0	0
T30	293879	12624	0	0
T31	12474	208	0	0
T32	10209	112	0	0
T34	0	116	0	0
T35	0	590	0	0
T37	7513	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	587174254	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	587174254	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	587174254	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	43837461	0	0
T3	11814	3371	0	0
T4	156637	860	0	0
T25	2280	0	0	0
T27	8551	1502	0	0
T28	10274	93	0	0
T29	8078	103	0	0
T30	293879	12624	0	0
T31	12474	208	0	0
T32	10209	112	0	0
T34	0	116	0	0
T35	0	590	0	0
T37	7513	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	589327825	20053119	0	0
DepthKnown_A	589327825	589001746	0	0
RvalidKnown_A	589327825	589001746	0	0
WreadyKnown_A	589327825	589001746	0	0
gen_passthru_fifo.paramCheckPass	3738	3738	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	20053119	0	0
T1	3791	5	0	0
T2	7618	10	0	0
T3	11814	12	0	0
T4	156637	20977	0	0
T25	2280	5	0	0
T27	8551	16	0	0
T28	10274	14	0	0
T29	8078	13	0	0
T30	293879	3750	0	0
T37	7513	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	589001746	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	589001746	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	589001746	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3738	3738	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T25	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T37	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	589327825	28352974	0	0
DepthKnown_A	589327825	589001746	0	0
RvalidKnown_A	589327825	589001746	0	0
WreadyKnown_A	589327825	589001746	0	0
gen_passthru_fifo.paramCheckPass	3738	3738	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	28352974	0	0
T1	3791	5	0	0
T2	7618	10	0	0
T3	11814	62	0	0
T4	156637	20977	0	0
T25	2280	13	0	0
T27	8551	55	0	0
T28	10274	14	0	0
T29	8078	13	0	0
T30	293879	13891	0	0
T37	7513	70	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	589001746	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	589001746	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	589001746	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3738	3738	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T25	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T37	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	589327825	935017	0	0
DepthKnown_A	589327825	589001746	0	0
RvalidKnown_A	589327825	589001746	0	0
WreadyKnown_A	589327825	589001746	0	0
gen_passthru_fifo.paramCheckPass	3738	3738	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	935017	0	0
T23	0	91	0	0
T25	2280	0	0	0
T29	8078	1	0	0
T30	293879	2461	0	0
T31	12474	33	0	0
T32	10209	16	0	0
T33	9482	0	0	0
T34	424027	0	0	0
T35	0	62	0	0
T36	0	123	0	0
T37	7513	0	0	0
T46	0	58	0	0
T59	237779	0	0	0
T76	0	56	0	0
T91	17900	0	0	0
T92	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	589001746	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	589001746	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	589001746	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3738	3738	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T25	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T37	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	589327825	1754007	0	0
DepthKnown_A	589327825	589001746	0	0
RvalidKnown_A	589327825	589001746	0	0
WreadyKnown_A	589327825	589001746	0	0
gen_passthru_fifo.paramCheckPass	3738	3738	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	1754007	0	0
T23	0	91	0	0
T25	2280	0	0	0
T29	8078	1	0	0
T30	293879	11256	0	0
T31	12474	157	0	0
T32	10209	46	0	0
T33	9482	0	0	0
T34	424027	0	0	0
T35	0	62	0	0
T36	0	123	0	0
T37	7513	0	0	0
T46	0	58	0	0
T59	237779	0	0	0
T76	0	238	0	0
T91	17900	0	0	0
T92	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	589001746	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	589001746	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	589001746	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3738	3738	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T25	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T37	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	589327825	19055816	0	0
DepthKnown_A	589327825	589001746	0	0
RvalidKnown_A	589327825	589001746	0	0
WreadyKnown_A	589327825	589001746	0	0
gen_passthru_fifo.paramCheckPass	3738	3738	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	19055816	0	0
T1	3791	5	0	0
T2	7618	10	0	0
T3	11814	12	0	0
T4	156637	20977	0	0
T25	2280	5	0	0
T27	8551	16	0	0
T28	10274	14	0	0
T29	8078	12	0	0
T30	293879	528	0	0
T37	7513	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	589001746	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	589001746	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	589001746	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3738	3738	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T25	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T37	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	589327825	26598967	0	0
DepthKnown_A	589327825	589001746	0	0
RvalidKnown_A	589327825	589001746	0	0
WreadyKnown_A	589327825	589001746	0	0
gen_passthru_fifo.paramCheckPass	3738	3738	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	26598967	0	0
T1	3791	5	0	0
T2	7618	10	0	0
T3	11814	62	0	0
T4	156637	20977	0	0
T25	2280	13	0	0
T27	8551	55	0	0
T28	10274	14	0	0
T29	8078	12	0	0
T30	293879	2635	0	0
T37	7513	70	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	589001746	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	589001746	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589327825	589001746	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3738	3738	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T25	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T37	1	1	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T29,T30,T31

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T29,T30,T31

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T29,T30,T31
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T29,T30,T31

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T29,T30,T31
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	587461143	1699941	0	0
DepthKnown_A	587461143	587174254	0	0
RvalidKnown_A	587461143	587174254	0	0
WreadyKnown_A	587461143	587174254	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	587461143	1699941	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	1699941	0	0
T23	0	91	0	0
T25	2280	0	0	0
T29	8078	1	0	0
T30	293879	11256	0	0
T31	12474	157	0	0
T32	10209	46	0	0
T33	9482	0	0	0
T34	424027	0	0	0
T35	0	62	0	0
T36	0	123	0	0
T37	7513	0	0	0
T46	0	58	0	0
T59	237779	0	0	0
T76	0	238	0	0
T91	17900	0	0	0
T92	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	587174254	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	587174254	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	587174254	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	1699941	0	0
T23	0	91	0	0
T25	2280	0	0	0
T29	8078	1	0	0
T30	293879	11256	0	0
T31	12474	157	0	0
T32	10209	46	0	0
T33	9482	0	0	0
T34	424027	0	0	0
T35	0	62	0	0
T36	0	123	0	0
T37	7513	0	0	0
T46	0	58	0	0
T59	237779	0	0	0
T76	0	238	0	0
T91	17900	0	0	0
T92	0	8	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T29,T30,T31

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T29,T30,T31

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T29,T30,T31

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T29,T30,T31
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	587461143	599116	0	0
DepthKnown_A	587461143	587174254	0	0
RvalidKnown_A	587461143	587174254	0	0
WreadyKnown_A	587461143	587174254	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	587461143	599116	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	599116	0	0
T23	0	91	0	0
T25	2280	0	0	0
T29	8078	1	0	0
T30	293879	1556	0	0
T31	12474	17	0	0
T32	10209	16	0	0
T33	9482	0	0	0
T34	424027	0	0	0
T35	0	39	0	0
T36	0	123	0	0
T37	7513	0	0	0
T46	0	40	0	0
T59	237779	0	0	0
T76	0	33	0	0
T79	0	45	0	0
T91	17900	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	587174254	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	587174254	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	587174254	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	599116	0	0
T23	0	91	0	0
T25	2280	0	0	0
T29	8078	1	0	0
T30	293879	1556	0	0
T31	12474	17	0	0
T32	10209	16	0	0
T33	9482	0	0	0
T34	424027	0	0	0
T35	0	39	0	0
T36	0	123	0	0
T37	7513	0	0	0
T46	0	40	0	0
T59	237779	0	0	0
T76	0	33	0	0
T79	0	45	0	0
T91	17900	0	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	18	18	100.00
Logical	18	18	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T29,T30,T31

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T29,T30,T31

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T29,T30,T31
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T29,T30,T31

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T29,T30,T31

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T32
1	0	Covered	T29,T30,T31
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T29,T30,T31
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	587461143	1157218	0	0
DepthKnown_A	587461143	587174254	0	0
RvalidKnown_A	587461143	587174254	0	0
WreadyKnown_A	587461143	587174254	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	587461143	1157218	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	1157218	0	0
T23	0	91	0	0
T25	2280	0	0	0
T29	8078	1	0	0
T30	293879	7031	0	0
T31	12474	62	0	0
T32	10209	46	0	0
T33	9482	0	0	0
T34	424027	0	0	0
T35	0	39	0	0
T36	0	123	0	0
T37	7513	0	0	0
T46	0	40	0	0
T59	237779	0	0	0
T76	0	136	0	0
T79	0	196	0	0
T91	17900	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	587174254	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	587174254	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	587174254	0	0
T1	3791	3704	0	0
T2	7618	7531	0	0
T3	11814	11750	0	0
T4	156637	156553	0	0
T25	2280	2191	0	0
T27	8551	8499	0	0
T28	10274	10209	0	0
T29	8078	8016	0	0
T30	293879	293783	0	0
T37	7513	7419	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	587461143	1157218	0	0
T23	0	91	0	0
T25	2280	0	0	0
T29	8078	1	0	0
T30	293879	7031	0	0
T31	12474	62	0	0
T32	10209	46	0	0
T33	9482	0	0	0
T34	424027	0	0	0
T35	0	39	0	0
T36	0	123	0	0
T37	7513	0	0	0
T46	0	40	0	0
T59	237779	0	0	0
T76	0	136	0	0
T79	0	196	0	0
T91	17900	0	0	0