Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9650854	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10235612

1

T1

11

T2

5

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19239578	1			T1	12		T2	3		T3	2
values[0x0]	323263	1			T1	13		T2	2		T3	4
values[0x1]	323625	1			T1	6		T2	7		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7670845	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

12215621

1

T1

18

T2

7

T3

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	103514	1			T29	1		T35	1		T37	2
valid_sources[0x01]	101154	1			T31	1		T37	10		T38	1
valid_sources[0x02]	111588	1			T37	6		T5	288		T7	1
valid_sources[0x03]	59291	1			T31	1		T37	8		T5	267
valid_sources[0x04]	112247	1			T4	53517		T37	6		T38	2
valid_sources[0x05]	109681	1			T37	11		T5	298		T6	95
valid_sources[0x06]	59368	1			T37	2		T5	270		T17	1
valid_sources[0x07]	78052	1			T37	9		T5	301		T17	1
valid_sources[0x08]	56937	1			T37	10		T47	7		T5	256
valid_sources[0x09]	58587	1			T37	5		T47	2		T5	270
valid_sources[0x0a]	81949	1			T31	1		T37	4		T5	303
valid_sources[0x0b]	57735	1			T37	3		T38	1		T47	4
valid_sources[0x0c]	58086	1			T31	1		T37	11		T38	3
valid_sources[0x0d]	73782	1			T37	5		T38	1		T47	1
valid_sources[0x0e]	120723	1			T29	2		T31	4		T37	12
valid_sources[0x0f]	59372	1			T31	1		T40	1		T37	7
valid_sources[0x10]	70368	1			T1	7		T31	1		T37	3
valid_sources[0x11]	58450	1			T36	1		T37	5		T38	1
valid_sources[0x12]	64989	1			T31	5		T37	8		T5	299
valid_sources[0x13]	126812	1			T31	1		T37	2		T5	304
valid_sources[0x14]	61322	1			T29	1		T31	1		T36	1
valid_sources[0x15]	96536	1			T35	10		T37	4		T5	287
valid_sources[0x16]	56775	1			T29	1		T37	5		T47	2
valid_sources[0x17]	57332	1			T31	1		T37	10		T5	276
valid_sources[0x18]	59744	1			T29	1		T37	5		T131	2
valid_sources[0x19]	58742	1			T37	5		T5	270		T7	1
valid_sources[0x1a]	59759	1			T37	10		T47	7		T5	275
valid_sources[0x1b]	57532	1			T37	3		T5	285		T6	94
valid_sources[0x1c]	58043	1			T1	9		T37	1		T38	1
valid_sources[0x1d]	57810	1			T29	1		T37	6		T38	2
valid_sources[0x1e]	59314	1			T2	2		T31	1		T37	7
valid_sources[0x1f]	73293	1			T1	7		T37	4		T5	307
valid_sources[0x20]	65397	1			T35	2		T37	9		T47	9
valid_sources[0x21]	58468	1			T31	5		T37	8		T5	275
valid_sources[0x22]	77916	1			T29	1		T31	1		T33	24
valid_sources[0x23]	60172	1			T31	1		T37	9		T5	294
valid_sources[0x24]	69142	1			T72	1		T37	9		T5	256
valid_sources[0x25]	59912	1			T31	1		T37	10		T5	286
valid_sources[0x26]	196590	1			T39	481		T40	3		T37	7
valid_sources[0x27]	59331	1			T1	1		T31	1		T35	1
valid_sources[0x28]	58345	1			T29	1		T31	2		T37	6
valid_sources[0x29]	68461	1			T31	2		T37	9		T5	254
valid_sources[0x2a]	58918	1			T35	4		T37	5		T47	2
valid_sources[0x2b]	59135	1			T31	1		T37	10		T5	284
valid_sources[0x2c]	59063	1			T72	1		T37	8		T88	26
valid_sources[0x2d]	179625	1			T31	5		T37	5		T47	6
valid_sources[0x2e]	57737	1			T29	2		T31	2		T37	4
valid_sources[0x2f]	72726	1			T40	1		T37	6		T5	280
valid_sources[0x30]	114410	1			T37	4		T131	1		T47	4
valid_sources[0x31]	81161	1			T30	1		T36	1		T37	4
valid_sources[0x32]	57584	1			T31	2		T37	11		T38	1
valid_sources[0x33]	58560	1			T31	1		T37	7		T5	288
valid_sources[0x34]	59786	1			T40	1		T37	3		T38	1
valid_sources[0x35]	57053	1			T31	1		T72	1		T37	9
valid_sources[0x36]	58002	1			T37	7		T5	300		T6	110
valid_sources[0x37]	102415	1			T37	5		T38	1		T5	284
valid_sources[0x38]	91704	1			T37	4		T5	284		T7	1
valid_sources[0x39]	56940	1			T31	1		T37	7		T5	286
valid_sources[0x3a]	206492	1			T29	1		T31	1		T35	11
valid_sources[0x3b]	101470	1			T31	2		T37	5		T5	283
valid_sources[0x3c]	56924	1			T29	1		T31	1		T37	6
valid_sources[0x3d]	57675	1			T37	7		T47	5		T5	278
valid_sources[0x3e]	57016	1			T29	1		T31	1		T37	10
valid_sources[0x3f]	108003	1			T37	6		T47	4		T5	275
valid_sources[0x40]	87343	1			T29	1		T30	1		T37	8
valid_sources[0x41]	58468	1			T37	5		T38	4		T5	284
valid_sources[0x42]	57975	1			T31	3		T37	4		T5	291
valid_sources[0x43]	60851	1			T37	6		T5	280		T6	92
valid_sources[0x44]	58538	1			T31	1		T37	5		T5	276
valid_sources[0x45]	57780	1			T36	1		T37	9		T38	2
valid_sources[0x46]	82008	1			T34	11		T37	5		T5	263
valid_sources[0x47]	58714	1			T37	11		T38	1		T5	272
valid_sources[0x48]	58506	1			T37	5		T5	286		T6	82
valid_sources[0x49]	56847	1			T37	12		T5	286		T7	3
valid_sources[0x4a]	160339	1			T29	1		T37	7		T38	5
valid_sources[0x4b]	57825	1			T37	4		T5	319		T20	1
valid_sources[0x4c]	59442	1			T3	9		T37	7		T47	1
valid_sources[0x4d]	73629	1			T37	6		T38	1		T5	269
valid_sources[0x4e]	58080	1			T31	1		T37	8		T5	288
valid_sources[0x4f]	58308	1			T35	1		T37	8		T5	271
valid_sources[0x50]	56908	1			T36	1		T37	6		T47	1
valid_sources[0x51]	75805	1			T31	2		T37	4		T47	1
valid_sources[0x52]	57616	1			T37	9		T38	1		T5	289
valid_sources[0x53]	59350	1			T31	1		T34	7		T37	4
valid_sources[0x54]	74182	1			T37	7		T5	309		T7	1
valid_sources[0x55]	58543	1			T72	1		T37	8		T47	4
valid_sources[0x56]	59022	1			T37	4		T38	1		T5	283
valid_sources[0x57]	128175	1			T29	2		T37	7		T38	2
valid_sources[0x58]	58075	1			T31	1		T37	6		T5	279
valid_sources[0x59]	172748	1			T37	3		T5	294		T7	2
valid_sources[0x5a]	57949	1			T37	7		T5	257		T7	2
valid_sources[0x5b]	71880	1			T37	3		T5	292		T17	2
valid_sources[0x5c]	59385	1			T31	1		T37	13		T5	312
valid_sources[0x5d]	59068	1			T37	11		T47	6		T5	311
valid_sources[0x5e]	57225	1			T37	6		T47	5		T5	279
valid_sources[0x5f]	87415	1			T35	5		T37	5		T5	266
valid_sources[0x60]	80731	1			T31	1		T37	6		T5	262
valid_sources[0x61]	73400	1			T2	1		T37	6		T5	256
valid_sources[0x62]	63597	1			T31	1		T37	6		T5	290
valid_sources[0x63]	117880	1			T31	1		T37	11		T5	282
valid_sources[0x64]	69252	1			T31	3		T37	9		T5	275
valid_sources[0x65]	120784	1			T37	6		T5	253		T6	104
valid_sources[0x66]	58536	1			T37	4		T5	268		T7	2
valid_sources[0x67]	57093	1			T36	1		T37	8		T5	251
valid_sources[0x68]	64223	1			T35	2		T37	3		T5	248
valid_sources[0x69]	75555	1			T36	2		T37	11		T5	255
valid_sources[0x6a]	57164	1			T72	1		T37	5		T5	288
valid_sources[0x6b]	58808	1			T31	2		T37	11		T5	276
valid_sources[0x6c]	67390	1			T37	6		T47	6		T5	277
valid_sources[0x6d]	74143	1			T37	10		T5	301		T6	95
valid_sources[0x6e]	57941	1			T37	3		T5	282		T17	1
valid_sources[0x6f]	56905	1			T72	1		T37	7		T38	1
valid_sources[0x70]	81411	1			T31	1		T37	5		T5	288
valid_sources[0x71]	120322	1			T37	6		T5	257		T17	1
valid_sources[0x72]	75675	1			T31	1		T37	8		T5	303
valid_sources[0x73]	56697	1			T31	1		T37	3		T47	3
valid_sources[0x74]	74550	1			T37	7		T5	328		T17	1
valid_sources[0x75]	57823	1			T31	2		T37	4		T131	1
valid_sources[0x76]	57942	1			T37	3		T5	271		T6	111
valid_sources[0x77]	58771	1			T31	1		T35	7		T37	7
valid_sources[0x78]	58299	1			T37	7		T5	278		T20	1
valid_sources[0x79]	59225	1			T31	1		T40	2		T37	10
valid_sources[0x7a]	128958	1			T40	1		T37	4		T5	274
valid_sources[0x7b]	59846	1			T31	1		T35	9		T37	4
valid_sources[0x7c]	195976	1			T2	2		T37	7		T5	291
valid_sources[0x7d]	135381	1			T30	3		T37	7		T5	273
valid_sources[0x7e]	134076	1			T31	1		T37	6		T47	7
valid_sources[0x7f]	68139	1			T31	2		T40	1		T37	6
valid_sources[0x80]	60420	1			T31	1		T37	5		T38	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9711515

1

T2

1

T3

1

T39

47

values[0x0]

all_enables

biggest_size

270851

1

T1

7

T2

1

T3

2

values[0x1]

all_enables

biggest_size

253246

1

T1

4

T2

3

T3

2