Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

9663322

1

T1

20

T2

7

T3

4

full_word

10236527

1

T1

11

T2

5

T3

5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	19899529	1			T1	31		T2	12		T3	9
auto[TlIntgErrCmd]	108	1			T262	7		T272	6		T273	5
auto[TlIntgErrData]	104	1			T262	8		T272	5		T273	4
auto[TlIntgErrBoth]	108	1			T262	5		T272	9		T273	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19241291

1

T1

12

T2

3

T3

2

auto[1]

658558

1

T1

19

T2

9

T3

7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9529473	1			T1	12		T2	2		T3	1
auto[TlIntgErrNone]	partial	auto[1]	133556	1			T1	8		T2	5		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	9711664	1			T2	1		T3	1		T39	47
auto[TlIntgErrNone]	full_word	auto[1]	524836	1			T1	11		T2	4		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T262	4		T272	3		T273	2
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T262	3		T272	3		T273	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T378	1		T379	1		T375	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T373	2		T380	1		T379	2
auto[TlIntgErrData]	partial	auto[0]	52	1			T262	6		T272	3		T273	3
auto[TlIntgErrData]	partial	auto[1]	45	1			T262	2		T272	2		T273	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T377	1		T380	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T327	1		T381	3		T382	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T272	6		T273	1		T327	3
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T262	4		T272	3		T327	6
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T377	1		T383	1		T381	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T262	1		T327	1		T384	1