Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	590803413	10168	0	0
ep_in_enable_rd_A	590803413	2494	0	0
ep_out_enable_rd_A	590803413	2486	0	0
in_iso_rd_A	590803413	2311	0	0
intr_enable_rd_A	590803413	3222	0	0
out_iso_rd_A	590803413	2465	0	0
phy_config_rd_A	590803413	1510	0	0
phy_pins_drive_rd_A	590803413	2234	0	0
rxenable_setup_rd_A	590803413	2553	0	0
set_nak_out_rd_A	590803413	2353	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590803413	10168	0	0
T223	8575	347	0	0
T224	4582	16	0	0
T225	5038	8	0	0
T261	3312	424	0	0
T262	63178	7	0	0
T269	10148	809	0	0
T272	61083	4	0	0
T278	5778	1049	0	0
T279	7698	344	0	0
T283	7165	18	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590803413	2494	0	0
T273	23830	97	0	0
T283	7165	43	0	0
T305	3551	4	0	0
T306	3173	7	0	0
T307	2355	3	0	0
T318	8819	43	0	0
T327	45325	192	0	0
T328	22188	380	0	0
T329	7804	65	0	0
T330	11637	36	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590803413	2486	0	0
T273	23830	149	0	0
T283	7165	75	0	0
T305	3551	2	0	0
T318	8819	32	0	0
T327	45325	324	0	0
T328	22188	297	0	0
T329	7804	104	0	0
T330	11637	30	0	0
T331	7530	3	0	0
T332	8054	15	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590803413	2311	0	0
T273	23830	92	0	0
T283	7165	86	0	0
T305	3551	20	0	0
T306	3173	6	0	0
T307	2355	1	0	0
T318	8819	23	0	0
T327	45325	236	0	0
T328	22188	176	0	0
T329	7804	110	0	0
T330	11637	14	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590803413	3222	0	0
T232	2876	18	0	0
T235	2065	6	0	0
T273	23830	160	0	0
T283	7165	56	0	0
T318	8819	36	0	0
T327	45325	337	0	0
T333	3530	29	0	0
T334	2039	23	0	0
T335	2259	6	0	0
T336	4942	18	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590803413	2465	0	0
T273	23830	145	0	0
T283	7165	71	0	0
T305	3551	65	0	0
T307	2355	11	0	0
T318	8819	15	0	0
T327	45325	237	0	0
T328	22188	332	0	0
T329	7804	55	0	0
T330	11637	40	0	0
T331	7530	4	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590803413	1510	0	0
T273	23830	55	0	0
T283	7165	25	0	0
T305	3551	12	0	0
T306	3173	2	0	0
T307	2355	4	0	0
T318	8819	33	0	0
T327	45325	161	0	0
T328	22188	155	0	0
T329	7804	38	0	0
T330	11637	32	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590803413	2234	0	0
T273	23830	101	0	0
T283	7165	45	0	0
T305	3551	31	0	0
T306	3173	5	0	0
T318	8819	25	0	0
T327	45325	213	0	0
T328	22188	207	0	0
T329	7804	91	0	0
T330	11637	26	0	0
T331	7530	11	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590803413	2553	0	0
T273	23830	144	0	0
T283	7165	44	0	0
T305	3551	19	0	0
T306	3173	9	0	0
T307	2355	39	0	0
T318	8819	33	0	0
T327	45325	194	0	0
T328	22188	383	0	0
T329	7804	124	0	0
T330	11637	48	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590803413	2353	0	0
T273	23830	199	0	0
T283	7165	50	0	0
T306	3173	7	0	0
T307	2355	1	0	0
T318	8819	21	0	0
T327	45325	206	0	0
T328	22188	123	0	0
T329	7804	53	0	0
T330	11637	61	0	0
T331	7530	2	0	0