Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9548939	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10156981

1

T1

32041

T2

74

T3

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19072654	1			T1	63515		T2	58		T3	19
values[0x0]	316302	1			T1	91		T2	34		T3	6
values[0x1]	316964	1			T1	101		T2	27		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7592145	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

12113775

1

T1

38263

T2

83

T3

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	110451	1			T1	259		T2	1		T27	9
valid_sources[0x01]	61274	1			T1	297		T27	19		T29	4
valid_sources[0x02]	85237	1			T1	212		T27	13		T31	20
valid_sources[0x03]	61593	1			T1	195		T27	16		T29	6
valid_sources[0x04]	61248	1			T1	251		T27	13		T31	23
valid_sources[0x05]	76223	1			T1	277		T27	14		T31	27
valid_sources[0x06]	79531	1			T1	299		T27	22		T31	24
valid_sources[0x07]	61601	1			T1	281		T2	2		T27	22
valid_sources[0x08]	61168	1			T1	257		T27	27		T31	21
valid_sources[0x09]	71530	1			T1	285		T3	1		T27	10
valid_sources[0x0a]	59361	1			T1	202		T27	8		T31	34
valid_sources[0x0b]	60682	1			T1	250		T27	28		T31	22
valid_sources[0x0c]	105100	1			T1	200		T2	3		T27	13
valid_sources[0x0d]	100422	1			T1	275		T2	1		T27	43
valid_sources[0x0e]	87642	1			T1	243		T2	1		T27	25
valid_sources[0x0f]	59927	1			T1	201		T2	1		T27	6
valid_sources[0x10]	89434	1			T1	244		T2	1		T27	41
valid_sources[0x11]	60657	1			T1	225		T2	1		T27	37
valid_sources[0x12]	61295	1			T1	234		T2	1		T27	17
valid_sources[0x13]	83744	1			T1	225		T27	39		T31	25
valid_sources[0x14]	60812	1			T1	236		T27	25		T31	20
valid_sources[0x15]	74986	1			T1	245		T2	1		T27	8
valid_sources[0x16]	61014	1			T1	223		T2	1		T27	13
valid_sources[0x17]	59889	1			T1	260		T27	19		T29	4
valid_sources[0x18]	65205	1			T1	179		T27	10		T31	32
valid_sources[0x19]	61388	1			T1	222		T27	7		T31	14
valid_sources[0x1a]	111050	1			T1	167		T2	1		T27	28
valid_sources[0x1b]	60010	1			T1	250		T3	1		T27	30
valid_sources[0x1c]	82614	1			T1	264		T2	1		T27	18
valid_sources[0x1d]	131029	1			T1	242		T2	1		T3	1
valid_sources[0x1e]	80107	1			T1	206		T27	10		T31	21
valid_sources[0x1f]	138643	1			T1	202		T27	15		T31	16
valid_sources[0x20]	67446	1			T1	255		T2	1		T27	7
valid_sources[0x21]	95189	1			T1	324		T2	1		T27	12
valid_sources[0x22]	116411	1			T1	279		T2	1		T27	6
valid_sources[0x23]	84324	1			T1	231		T2	1		T27	19
valid_sources[0x24]	60545	1			T1	252		T2	1		T27	11
valid_sources[0x25]	73063	1			T1	301		T27	54		T31	19
valid_sources[0x26]	60551	1			T1	222		T27	29		T31	33
valid_sources[0x27]	59848	1			T1	306		T27	22		T31	16
valid_sources[0x28]	60363	1			T1	233		T27	15		T31	13
valid_sources[0x29]	75579	1			T1	250		T3	2		T27	40
valid_sources[0x2a]	69431	1			T1	215		T2	1		T27	19
valid_sources[0x2b]	170973	1			T1	222		T27	5		T31	28
valid_sources[0x2c]	60502	1			T1	232		T2	1		T27	37
valid_sources[0x2d]	61933	1			T1	281		T2	1		T3	2
valid_sources[0x2e]	72760	1			T1	221		T27	23		T31	25
valid_sources[0x2f]	61111	1			T1	229		T27	12		T31	30
valid_sources[0x30]	96380	1			T1	260		T2	1		T27	13
valid_sources[0x31]	60271	1			T1	193		T3	1		T27	9
valid_sources[0x32]	60129	1			T1	228		T2	2		T27	18
valid_sources[0x33]	60904	1			T1	283		T27	48		T31	24
valid_sources[0x34]	72572	1			T1	276		T27	17		T31	18
valid_sources[0x35]	59578	1			T1	266		T27	19		T31	38
valid_sources[0x36]	79748	1			T1	239		T27	3		T30	34
valid_sources[0x37]	61189	1			T1	213		T2	1		T27	35
valid_sources[0x38]	60831	1			T1	220		T2	1		T27	21
valid_sources[0x39]	60868	1			T1	262		T3	1		T27	22
valid_sources[0x3a]	105894	1			T1	232		T27	7		T31	26
valid_sources[0x3b]	60928	1			T1	239		T2	1		T27	10
valid_sources[0x3c]	61773	1			T1	259		T27	21		T31	31
valid_sources[0x3d]	62365	1			T1	237		T27	19		T31	23
valid_sources[0x3e]	178804	1			T1	249		T2	1		T27	9
valid_sources[0x3f]	60585	1			T1	246		T27	16		T29	3
valid_sources[0x40]	61894	1			T1	243		T27	34		T31	19
valid_sources[0x41]	151216	1			T1	211		T27	29		T31	28
valid_sources[0x42]	101785	1			T1	287		T2	2		T27	8
valid_sources[0x43]	61295	1			T1	240		T27	10		T31	38
valid_sources[0x44]	60063	1			T1	322		T2	1		T27	24
valid_sources[0x45]	60724	1			T1	283		T27	32		T31	38
valid_sources[0x46]	107235	1			T1	269		T2	1		T27	20
valid_sources[0x47]	62252	1			T1	247		T3	1		T27	13
valid_sources[0x48]	62656	1			T1	192		T3	1		T27	20
valid_sources[0x49]	78166	1			T1	212		T27	9		T31	28
valid_sources[0x4a]	60482	1			T1	198		T2	2		T27	22
valid_sources[0x4b]	123354	1			T1	238		T2	2		T27	19
valid_sources[0x4c]	88312	1			T1	291		T2	1		T27	7
valid_sources[0x4d]	141087	1			T1	223		T27	14		T31	29
valid_sources[0x4e]	62217	1			T1	287		T27	6		T31	35
valid_sources[0x4f]	68194	1			T1	291		T27	18		T31	20
valid_sources[0x50]	75738	1			T1	230		T27	8		T31	32
valid_sources[0x51]	60772	1			T1	206		T3	1		T27	26
valid_sources[0x52]	209249	1			T1	225		T27	20		T31	22
valid_sources[0x53]	60461	1			T1	260		T27	17		T31	25
valid_sources[0x54]	60195	1			T1	239		T27	11		T31	19
valid_sources[0x55]	68803	1			T1	269		T27	2		T31	17
valid_sources[0x56]	61897	1			T1	204		T27	20		T31	31
valid_sources[0x57]	121318	1			T1	265		T27	16		T31	28
valid_sources[0x58]	60342	1			T1	286		T27	41		T31	27
valid_sources[0x59]	60482	1			T1	278		T27	13		T31	34
valid_sources[0x5a]	114554	1			T1	231		T3	1		T27	16
valid_sources[0x5b]	61146	1			T1	219		T27	23		T31	21
valid_sources[0x5c]	58958	1			T1	274		T27	12		T31	24
valid_sources[0x5d]	61550	1			T1	264		T2	1		T27	16
valid_sources[0x5e]	61538	1			T1	223		T27	12		T31	27
valid_sources[0x5f]	118059	1			T1	235		T2	1		T27	19
valid_sources[0x60]	60879	1			T1	252		T2	1		T27	30
valid_sources[0x61]	61288	1			T1	190		T27	19		T31	25
valid_sources[0x62]	60453	1			T1	225		T27	22		T31	19
valid_sources[0x63]	61116	1			T1	229		T2	3		T27	33
valid_sources[0x64]	60559	1			T1	260		T2	1		T27	20
valid_sources[0x65]	61136	1			T1	212		T2	1		T27	26
valid_sources[0x66]	69794	1			T1	277		T27	26		T31	27
valid_sources[0x67]	61046	1			T1	215		T2	1		T3	1
valid_sources[0x68]	60317	1			T1	267		T2	1		T27	3
valid_sources[0x69]	62594	1			T1	275		T2	1		T27	15
valid_sources[0x6a]	77574	1			T1	211		T27	8		T29	12
valid_sources[0x6b]	65871	1			T1	251		T2	1		T27	28
valid_sources[0x6c]	90015	1			T1	275		T34	11		T27	22
valid_sources[0x6d]	60905	1			T1	300		T2	1		T27	18
valid_sources[0x6e]	115932	1			T1	227		T27	20		T31	21
valid_sources[0x6f]	60637	1			T1	224		T2	1		T3	1
valid_sources[0x70]	189803	1			T1	242		T2	2		T27	13
valid_sources[0x71]	59812	1			T1	266		T27	16		T31	18
valid_sources[0x72]	60139	1			T1	250		T27	5		T31	22
valid_sources[0x73]	84360	1			T1	261		T27	37		T31	24
valid_sources[0x74]	60794	1			T1	226		T27	8		T31	22
valid_sources[0x75]	60465	1			T1	242		T27	25		T31	23
valid_sources[0x76]	61636	1			T1	285		T27	25		T31	23
valid_sources[0x77]	59515	1			T1	287		T2	2		T27	7
valid_sources[0x78]	59819	1			T1	264		T27	6		T31	19
valid_sources[0x79]	61288	1			T1	241		T27	13		T31	19
valid_sources[0x7a]	61593	1			T1	281		T2	2		T27	13
valid_sources[0x7b]	62369	1			T1	244		T27	19		T31	23
valid_sources[0x7c]	85980	1			T1	227		T2	1		T27	11
valid_sources[0x7d]	93016	1			T1	184		T27	21		T31	21
valid_sources[0x7e]	60098	1			T1	230		T2	1		T27	8
valid_sources[0x7f]	61307	1			T1	234		T27	6		T31	30
valid_sources[0x80]	72575	1			T1	219		T27	16		T31	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9640762

1

T1

31915

T2

35

T3

14

values[0x0]

all_enables

biggest_size

266551

1

T1

61

T2

23

T3

6

values[0x1]

all_enables

biggest_size

249668

1

T1

65

T2

16

T26

4