Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

9563068

1

T1

31666

T2

45

T3

10

full_word

10157886

1

T1

32041

T2

74

T3

20

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	19720674	1			T1	63707		T2	119		T3	30
auto[TlIntgErrCmd]	103	1			T220	4		T257	7		T260	2
auto[TlIntgErrData]	104	1			T220	2		T257	9		T260	4
auto[TlIntgErrBoth]	73	1			T220	4		T257	4		T260	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19074376

1

T1

63515

T2

58

T3

19

auto[1]

646578

1

T1

192

T2

61

T3

11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9433339	1			T1	31600		T2	23		T3	5
auto[TlIntgErrNone]	partial	auto[1]	129472	1			T1	66		T2	22		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	9640915	1			T1	31915		T2	35		T3	14
auto[TlIntgErrNone]	full_word	auto[1]	516948	1			T1	126		T2	39		T3	6
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T220	1		T257	2		T260	1
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T220	3		T257	4		T260	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T511	1		T514	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T257	1		T515	1		T516	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T220	1		T257	4		T260	2
auto[TlIntgErrData]	partial	auto[1]	53	1			T220	1		T257	5		T260	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T512	1		T509	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T515	1		T516	1		T517	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T220	3		T257	2		T260	2
auto[TlIntgErrBoth]	partial	auto[1]	30	1			T220	1		T257	2		T260	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T260	1		T513	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T511	2		T518	1		T514	1