Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	579634470	11313	0	0
ep_in_enable_rd_A	579634470	1856	0	0
ep_out_enable_rd_A	579634470	2139	0	0
in_iso_rd_A	579634470	2194	0	0
intr_enable_rd_A	579634470	2792	0	0
out_iso_rd_A	579634470	2020	0	0
phy_config_rd_A	579634470	1402	0	0
phy_pins_drive_rd_A	579634470	1748	0	0
rxenable_setup_rd_A	579634470	1943	0	0
set_nak_out_rd_A	579634470	1984	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579634470	11313	0	0
T218	4474	20	0	0
T219	5436	851	0	0
T220	19379	2	0	0
T253	10838	17	0	0
T257	49118	3	0	0
T261	3196	240	0	0
T262	4644	502	0	0
T263	6891	170	0	0
T270	3708	16	0	0
T271	3965	14	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579634470	1856	0	0
T253	10838	16	0	0
T255	4876	18	0	0
T266	7977	14	0	0
T286	8238	50	0	0
T287	3915	80	0	0
T289	4360	96	0	0
T294	4151	29	0	0
T302	6316	8	0	0
T308	18482	43	0	0
T309	3914	9	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579634470	2139	0	0
T253	10838	6	0	0
T255	4876	6	0	0
T266	7977	60	0	0
T286	8238	74	0	0
T287	3915	88	0	0
T289	4360	80	0	0
T294	4151	39	0	0
T302	6316	35	0	0
T308	18482	33	0	0
T309	3914	5	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579634470	2194	0	0
T253	10838	42	0	0
T255	4876	2	0	0
T266	7977	81	0	0
T286	8238	45	0	0
T287	3915	89	0	0
T289	4360	80	0	0
T294	4151	60	0	0
T302	6316	9	0	0
T308	18482	54	0	0
T309	3914	49	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579634470	2792	0	0
T222	2138	12	0	0
T224	2820	27	0	0
T227	2532	14	0	0
T253	10838	147	0	0
T255	4876	7	0	0
T286	8238	41	0	0
T287	3915	59	0	0
T294	4151	89	0	0
T302	6316	1	0	0
T310	2049	21	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579634470	2020	0	0
T253	10838	50	0	0
T266	7977	39	0	0
T272	9291	34	0	0
T286	8238	57	0	0
T287	3915	37	0	0
T289	4360	48	0	0
T294	4151	38	0	0
T302	6316	22	0	0
T308	18482	45	0	0
T309	3914	31	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579634470	1402	0	0
T253	10838	36	0	0
T255	4876	20	0	0
T266	7977	30	0	0
T272	9291	18	0	0
T286	8238	36	0	0
T287	3915	5	0	0
T289	4360	63	0	0
T294	4151	18	0	0
T302	6316	24	0	0
T308	18482	41	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579634470	1748	0	0
T253	10838	78	0	0
T255	4876	12	0	0
T266	7977	42	0	0
T286	8238	44	0	0
T287	3915	46	0	0
T289	4360	33	0	0
T294	4151	18	0	0
T302	6316	27	0	0
T308	18482	59	0	0
T309	3914	28	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579634470	1943	0	0
T253	10838	74	0	0
T255	4876	4	0	0
T266	7977	17	0	0
T286	8238	43	0	0
T287	3915	40	0	0
T289	4360	47	0	0
T294	4151	1	0	0
T302	6316	18	0	0
T308	18482	11	0	0
T309	3914	52	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579634470	1984	0	0
T253	10838	62	0	0
T255	4876	32	0	0
T266	7977	19	0	0
T272	9291	5	0	0
T286	8238	28	0	0
T287	3915	60	0	0
T289	4360	67	0	0
T294	4151	55	0	0
T308	18482	29	0	0
T309	3914	48	0	0