Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9655915	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10227075

1

T1

44997

T2

28

T3

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19237010	1			T1	90015		T2	35		T3	168
values[0x0]	323170	1			T1	119		T2	17		T3	6
values[0x1]	322810	1			T1	89		T2	17		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7673780	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

12209210

1

T1

54063

T2

39

T3

64

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	61713	1			T1	309		T4	227		T5	93
valid_sources[0x01]	73358	1			T1	333		T3	1		T4	216
valid_sources[0x02]	117598	1			T1	368		T4	209		T5	53
valid_sources[0x03]	81245	1			T1	381		T17	3		T21	1
valid_sources[0x04]	62200	1			T1	335		T3	2		T17	1
valid_sources[0x05]	61303	1			T1	343		T4	192		T5	69
valid_sources[0x06]	60507	1			T1	395		T18	24		T4	212
valid_sources[0x07]	62512	1			T1	340		T3	1		T17	4
valid_sources[0x08]	67625	1			T1	384		T17	1		T4	238
valid_sources[0x09]	91628	1			T1	341		T3	1		T17	3
valid_sources[0x0a]	76563	1			T1	345		T2	3		T4	223
valid_sources[0x0b]	76997	1			T1	357		T17	2		T4	213
valid_sources[0x0c]	81374	1			T1	349		T3	2		T17	86
valid_sources[0x0d]	60049	1			T1	369		T3	2		T4	248
valid_sources[0x0e]	60952	1			T1	342		T3	1		T17	6
valid_sources[0x0f]	164695	1			T1	339		T17	2		T4	240
valid_sources[0x10]	75298	1			T1	378		T3	1		T16	1
valid_sources[0x11]	62018	1			T1	347		T3	1		T17	137
valid_sources[0x12]	77278	1			T1	345		T16	1		T17	72
valid_sources[0x13]	61627	1			T1	337		T3	1		T17	1
valid_sources[0x14]	62039	1			T1	360		T17	6		T4	263
valid_sources[0x15]	60371	1			T1	325		T3	1		T17	2
valid_sources[0x16]	63672	1			T1	323		T3	1		T15	27
valid_sources[0x17]	60875	1			T1	317		T17	3		T4	209
valid_sources[0x18]	76535	1			T1	377		T17	3		T4	176
valid_sources[0x19]	93327	1			T1	340		T2	1		T17	2
valid_sources[0x1a]	74673	1			T1	385		T3	1		T16	1
valid_sources[0x1b]	65592	1			T1	337		T17	4		T4	273
valid_sources[0x1c]	62172	1			T1	372		T3	2		T17	2
valid_sources[0x1d]	62880	1			T1	338		T17	5		T20	1
valid_sources[0x1e]	61619	1			T1	337		T3	1		T17	2
valid_sources[0x1f]	61123	1			T1	352		T3	2		T17	259
valid_sources[0x20]	60274	1			T1	352		T20	1		T4	204
valid_sources[0x21]	130946	1			T1	385		T3	1		T22	4
valid_sources[0x22]	107791	1			T1	342		T3	1		T20	1
valid_sources[0x23]	59964	1			T1	339		T16	1		T17	2
valid_sources[0x24]	61854	1			T1	395		T17	1		T4	247
valid_sources[0x25]	62232	1			T1	361		T4	234		T5	17
valid_sources[0x26]	62274	1			T1	346		T17	2		T4	254
valid_sources[0x27]	108066	1			T1	366		T17	2		T4	247
valid_sources[0x28]	60921	1			T1	326		T17	879		T23	1
valid_sources[0x29]	61989	1			T1	357		T3	1		T17	185
valid_sources[0x2a]	60563	1			T1	335		T4	188		T5	42
valid_sources[0x2b]	61810	1			T1	354		T3	1		T17	1
valid_sources[0x2c]	60965	1			T1	380		T3	1		T4	194
valid_sources[0x2d]	61146	1			T1	319		T17	1		T4	233
valid_sources[0x2e]	60725	1			T1	366		T3	1		T17	3
valid_sources[0x2f]	60980	1			T1	391		T4	190		T5	53
valid_sources[0x30]	60879	1			T1	331		T23	1		T4	250
valid_sources[0x31]	60069	1			T1	346		T2	1		T3	1
valid_sources[0x32]	60760	1			T1	352		T20	4		T4	220
valid_sources[0x33]	76020	1			T1	346		T3	2		T17	2
valid_sources[0x34]	61141	1			T1	353		T17	202		T4	198
valid_sources[0x35]	61415	1			T1	336		T17	18		T4	211
valid_sources[0x36]	60588	1			T1	320		T3	1		T4	191
valid_sources[0x37]	62049	1			T1	290		T3	1		T17	1
valid_sources[0x38]	59839	1			T1	338		T17	27		T4	218
valid_sources[0x39]	62815	1			T1	350		T3	2		T17	6
valid_sources[0x3a]	63747	1			T1	381		T3	1		T17	2
valid_sources[0x3b]	60304	1			T1	355		T3	1		T17	4
valid_sources[0x3c]	60078	1			T1	380		T3	1		T17	3
valid_sources[0x3d]	87007	1			T1	366		T3	2		T17	3
valid_sources[0x3e]	152795	1			T1	364		T2	3		T3	2
valid_sources[0x3f]	60385	1			T1	345		T17	148		T20	1
valid_sources[0x40]	61125	1			T1	365		T3	1		T17	5
valid_sources[0x41]	121735	1			T1	360		T17	1		T4	198
valid_sources[0x42]	60902	1			T1	384		T17	98		T4	229
valid_sources[0x43]	104536	1			T1	378		T17	1		T18	81
valid_sources[0x44]	60319	1			T1	354		T17	3		T20	1
valid_sources[0x45]	73748	1			T1	357		T3	3		T17	184
valid_sources[0x46]	61440	1			T1	356		T17	7		T21	1
valid_sources[0x47]	100667	1			T1	345		T3	2		T17	2
valid_sources[0x48]	61987	1			T1	333		T3	1		T4	229
valid_sources[0x49]	60376	1			T1	377		T17	2		T4	204
valid_sources[0x4a]	61820	1			T1	360		T17	1		T4	240
valid_sources[0x4b]	60244	1			T1	391		T3	3		T4	229
valid_sources[0x4c]	61482	1			T1	324		T3	1		T17	2
valid_sources[0x4d]	80202	1			T1	329		T17	4		T4	227
valid_sources[0x4e]	61358	1			T1	330		T16	1		T17	4
valid_sources[0x4f]	116296	1			T1	333		T17	3		T4	259
valid_sources[0x50]	61279	1			T1	353		T3	1		T17	2
valid_sources[0x51]	62071	1			T1	332		T3	1		T4	222
valid_sources[0x52]	60719	1			T1	331		T3	1		T17	1
valid_sources[0x53]	75794	1			T1	342		T17	95		T20	1
valid_sources[0x54]	64775	1			T1	356		T3	1		T4	193
valid_sources[0x55]	60820	1			T1	312		T17	1		T21	1
valid_sources[0x56]	61808	1			T1	356		T3	1		T17	253
valid_sources[0x57]	70846	1			T1	348		T3	1		T17	2
valid_sources[0x58]	97402	1			T1	367		T3	4		T18	19
valid_sources[0x59]	63069	1			T1	336		T17	3		T4	224
valid_sources[0x5a]	61283	1			T1	318		T17	3		T4	278
valid_sources[0x5b]	60668	1			T1	345		T3	1		T17	4
valid_sources[0x5c]	62405	1			T1	419		T3	2		T4	260
valid_sources[0x5d]	71402	1			T1	345		T3	1		T17	4
valid_sources[0x5e]	152878	1			T1	390		T20	2		T21	1
valid_sources[0x5f]	68264	1			T1	352		T3	1		T4	213
valid_sources[0x60]	63297	1			T1	368		T3	1		T17	4
valid_sources[0x61]	61532	1			T1	374		T3	1		T17	2
valid_sources[0x62]	61154	1			T1	336		T21	1		T4	226
valid_sources[0x63]	72527	1			T1	347		T17	4		T20	1
valid_sources[0x64]	60830	1			T1	370		T2	3		T3	1
valid_sources[0x65]	63327	1			T1	380		T3	1		T4	236
valid_sources[0x66]	60396	1			T1	387		T3	4		T17	1
valid_sources[0x67]	62158	1			T1	363		T17	4		T21	1
valid_sources[0x68]	64485	1			T1	377		T3	1		T17	5
valid_sources[0x69]	71456	1			T1	340		T4	255		T5	51
valid_sources[0x6a]	81319	1			T1	341		T3	1		T17	2
valid_sources[0x6b]	77982	1			T1	319		T17	1		T4	271
valid_sources[0x6c]	128120	1			T1	358		T2	3		T17	3
valid_sources[0x6d]	61057	1			T1	356		T17	2		T4	232
valid_sources[0x6e]	82860	1			T1	340		T3	1		T17	65
valid_sources[0x6f]	60468	1			T1	371		T3	2		T17	127
valid_sources[0x70]	74487	1			T1	312		T3	1		T17	3
valid_sources[0x71]	106011	1			T1	301		T3	1		T4	264
valid_sources[0x72]	61816	1			T1	354		T17	2		T4	231
valid_sources[0x73]	60666	1			T1	369		T17	3		T4	199
valid_sources[0x74]	62845	1			T1	345		T2	2		T17	4
valid_sources[0x75]	61197	1			T1	381		T3	1		T17	2
valid_sources[0x76]	84837	1			T1	361		T2	3		T3	1
valid_sources[0x77]	61065	1			T1	375		T4	188		T5	29
valid_sources[0x78]	61382	1			T1	370		T3	1		T17	4
valid_sources[0x79]	83843	1			T1	300		T4	253		T5	61
valid_sources[0x7a]	61997	1			T1	343		T3	2		T17	2
valid_sources[0x7b]	86474	1			T1	343		T17	5		T20	1
valid_sources[0x7c]	108429	1			T1	372		T3	3		T17	1
valid_sources[0x7d]	63096	1			T1	358		T17	209		T4	189
valid_sources[0x7e]	60243	1			T1	400		T3	2		T17	2
valid_sources[0x7f]	60142	1			T1	373		T17	1		T4	206
valid_sources[0x80]	67630	1			T1	347		T4	273		T5	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9703873

1

T1

44854

T2

5

T3

2

values[0x0]

all_enables

biggest_size

270967

1

T1

86

T2

11

T3

4

values[0x1]

all_enables

biggest_size

252235

1

T1

57

T2

12

T3

5