Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

9668587

1

T1

45226

T2

41

T3

173

full_word

10227857

1

T1

44997

T2

28

T3

11

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	19896124	1			T1	90223		T2	69		T3	184
auto[TlIntgErrCmd]	118	1			T235	8		T268	1		T275	8
auto[TlIntgErrData]	105	1			T235	6		T268	5		T275	8
auto[TlIntgErrBoth]	97	1			T235	6		T268	4		T275	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19238595

1

T1

90015

T2

35

T3

168

auto[1]

657849

1

T1

208

T2

34

T3

16

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9534431	1			T1	45161		T2	30		T3	166
auto[TlIntgErrNone]	partial	auto[1]	133866	1			T1	65		T2	11		T3	7
auto[TlIntgErrNone]	full_word	auto[0]	9704008	1			T1	44854		T2	5		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	523819	1			T1	143		T2	23		T3	9
auto[TlIntgErrCmd]	partial	auto[0]	56	1			T235	2		T268	1		T275	4
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T235	6		T275	3		T294	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T275	1		T507	1		T509	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T507	1		T509	1		T505	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T235	3		T268	2		T275	4
auto[TlIntgErrData]	partial	auto[1]	45	1			T235	2		T268	2		T275	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T510	1		T511	1		T506	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T235	1		T268	1		T512	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T235	4		T268	3		T275	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T235	2		T268	1		T275	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T294	1		T513	2		T505	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T504	1		T514	1		T513	1