Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	593504361	10098	0	0
ep_in_enable_rd_A	593504361	5519	0	0
ep_out_enable_rd_A	593504361	4981	0	0
in_iso_rd_A	593504361	5094	0	0
intr_enable_rd_A	593504361	7414	0	0
out_iso_rd_A	593504361	5213	0	0
phy_config_rd_A	593504361	3305	0	0
phy_pins_drive_rd_A	593504361	4154	0	0
rxenable_setup_rd_A	593504361	4717	0	0
set_nak_out_rd_A	593504361	4827	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	10098	0	0
T234	8966	13	0	0
T235	43253	4	0	0
T236	8720	17	0	0
T267	5544	819	0	0
T268	19251	5	0	0
T275	69378	3	0	0
T283	6441	8	0	0
T291	5468	7	0	0
T292	5600	8	0	0
T293	8206	23	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	5519	0	0
T235	43253	609	0	0
T236	8720	97	0	0
T268	19251	185	0	0
T275	69378	260	0	0
T283	6441	67	0	0
T291	5468	47	0	0
T292	5600	11	0	0
T293	8206	65	0	0
T302	3462	32	0	0
T304	3974	59	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	4981	0	0
T235	43253	412	0	0
T236	8720	112	0	0
T268	19251	288	0	0
T275	69378	249	0	0
T291	5468	48	0	0
T292	5600	36	0	0
T293	8206	123	0	0
T302	3462	42	0	0
T303	5039	6	0	0
T304	3974	63	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	5094	0	0
T235	43253	284	0	0
T236	8720	52	0	0
T268	19251	267	0	0
T275	69378	222	0	0
T291	5468	10	0	0
T292	5600	29	0	0
T293	8206	61	0	0
T302	3462	36	0	0
T303	5039	7	0	0
T304	3974	44	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	7414	0	0
T235	43253	695	0	0
T236	8720	155	0	0
T242	1995	6	0	0
T243	2243	13	0	0
T244	3537	14	0	0
T268	19251	254	0	0
T302	3462	40	0	0
T304	3974	15	0	0
T323	2444	6	0	0
T324	2334	28	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	5213	0	0
T235	43253	528	0	0
T236	8720	90	0	0
T268	19251	206	0	0
T275	69378	337	0	0
T283	6441	15	0	0
T291	5468	42	0	0
T292	5600	4	0	0
T293	8206	64	0	0
T302	3462	22	0	0
T304	3974	38	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	3305	0	0
T235	43253	268	0	0
T236	8720	40	0	0
T268	19251	218	0	0
T275	69378	192	0	0
T283	6441	6	0	0
T291	5468	25	0	0
T292	5600	17	0	0
T293	8206	35	0	0
T302	3462	30	0	0
T304	3974	14	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	4154	0	0
T235	43253	387	0	0
T236	8720	16	0	0
T268	19251	173	0	0
T275	69378	140	0	0
T279	9259	9	0	0
T283	6441	2	0	0
T291	5468	22	0	0
T292	5600	24	0	0
T293	8206	102	0	0
T304	3974	12	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	4717	0	0
T235	43253	463	0	0
T236	8720	86	0	0
T268	19251	302	0	0
T275	69378	262	0	0
T283	6441	43	0	0
T291	5468	3	0	0
T292	5600	3	0	0
T293	8206	92	0	0
T302	3462	16	0	0
T304	3974	5	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	4827	0	0
T235	43253	542	0	0
T236	8720	16	0	0
T268	19251	243	0	0
T275	69378	211	0	0
T291	5468	5	0	0
T292	5600	24	0	0
T293	8206	20	0	0
T302	3462	26	0	0
T303	5039	8	0	0
T304	3974	101	0	0