Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8393175	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9008113

1

T1

5

T2

19

T3

20881

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	16775364	1			T1	3		T2	15		T3	41743
values[0x0]	312120	1			T1	4		T2	7		T3	74
values[0x1]	313804	1			T1	5		T2	15		T3	69

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6668802	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

10732486

1

T1

7

T2

21

T3

25136

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	109636	1			T44	1		T68	6		T45	1
valid_sources[0x01]	50252	1			T5	172		T116	76		T197	56
valid_sources[0x02]	123074	1			T5	257		T116	80		T197	55
valid_sources[0x03]	49728	1			T35	9		T5	227		T116	80
valid_sources[0x04]	50605	1			T30	1		T35	7		T44	1
valid_sources[0x05]	49550	1			T33	1		T5	214		T89	1
valid_sources[0x06]	65988	1			T5	172		T116	91		T197	51
valid_sources[0x07]	50102	1			T31	2		T44	2		T45	1
valid_sources[0x08]	50894	1			T45	1		T5	184		T89	1
valid_sources[0x09]	84011	1			T90	4		T5	247		T89	1
valid_sources[0x0a]	48958	1			T33	1		T34	1		T35	10
valid_sources[0x0b]	92900	1			T33	1		T35	1		T45	2
valid_sources[0x0c]	49405	1			T5	171		T116	72		T197	56
valid_sources[0x0d]	63538	1			T33	2		T34	1		T45	1
valid_sources[0x0e]	50775	1			T28	1		T45	2		T5	222
valid_sources[0x0f]	70398	1			T34	1		T35	7		T44	1
valid_sources[0x10]	77845	1			T5	286		T116	66		T197	44
valid_sources[0x11]	90525	1			T44	1		T68	4		T45	2
valid_sources[0x12]	49322	1			T45	1		T5	181		T89	1
valid_sources[0x13]	81426	1			T30	19		T90	1		T45	4
valid_sources[0x14]	51491	1			T33	1		T5	241		T116	92
valid_sources[0x15]	58816	1			T44	1		T45	3		T5	180
valid_sources[0x16]	132014	1			T5	232		T116	85		T197	50
valid_sources[0x17]	63771	1			T33	1		T45	2		T5	307
valid_sources[0x18]	49691	1			T33	2		T34	1		T5	207
valid_sources[0x19]	49764	1			T45	1		T5	160		T116	95
valid_sources[0x1a]	70683	1			T35	4		T5	235		T116	84
valid_sources[0x1b]	120051	1			T34	5		T44	1		T5	153
valid_sources[0x1c]	56786	1			T33	1		T34	1		T45	1
valid_sources[0x1d]	144585	1			T5	249		T116	75		T197	41
valid_sources[0x1e]	49752	1			T30	2		T33	1		T34	9
valid_sources[0x1f]	70849	1			T33	1		T35	3		T90	1
valid_sources[0x20]	51023	1			T44	1		T5	259		T116	95
valid_sources[0x21]	109155	1			T34	2		T45	2		T5	215
valid_sources[0x22]	49208	1			T34	1		T45	6		T5	209
valid_sources[0x23]	110850	1			T44	1		T45	4		T5	217
valid_sources[0x24]	92822	1			T30	3		T33	1		T35	1
valid_sources[0x25]	49997	1			T5	213		T116	76		T197	58
valid_sources[0x26]	49486	1			T45	2		T5	224		T116	89
valid_sources[0x27]	72693	1			T34	2		T45	1		T5	226
valid_sources[0x28]	50841	1			T34	1		T45	2		T5	197
valid_sources[0x29]	133015	1			T90	1		T5	194		T116	83
valid_sources[0x2a]	67012	1			T33	2		T34	3		T44	1
valid_sources[0x2b]	51300	1			T44	1		T5	184		T116	77
valid_sources[0x2c]	88335	1			T5	182		T89	1		T116	81
valid_sources[0x2d]	75458	1			T29	2801		T35	1		T44	1
valid_sources[0x2e]	121858	1			T33	2		T5	293		T116	81
valid_sources[0x2f]	50371	1			T31	8		T34	2		T44	4
valid_sources[0x30]	49376	1			T30	24		T45	1		T5	137
valid_sources[0x31]	63018	1			T30	1		T45	3		T5	188
valid_sources[0x32]	63881	1			T28	4		T33	1		T35	5
valid_sources[0x33]	133941	1			T30	9		T33	1		T5	191
valid_sources[0x34]	50101	1			T44	1		T5	254		T116	91
valid_sources[0x35]	198383	1			T5	180		T89	1		T116	99
valid_sources[0x36]	50305	1			T33	2		T5	144		T116	89
valid_sources[0x37]	131000	1			T5	207		T116	102		T197	68
valid_sources[0x38]	87004	1			T5	168		T116	86		T197	68
valid_sources[0x39]	62994	1			T45	2		T5	204		T89	1
valid_sources[0x3a]	137746	1			T5	174		T116	82		T197	52
valid_sources[0x3b]	51087	1			T33	1		T5	207		T116	75
valid_sources[0x3c]	49621	1			T5	195		T89	1		T116	77
valid_sources[0x3d]	50246	1			T33	3		T44	1		T45	1
valid_sources[0x3e]	49727	1			T45	3		T5	160		T116	79
valid_sources[0x3f]	83792	1			T35	2		T44	3		T68	1
valid_sources[0x40]	50138	1			T33	1		T35	1		T45	3
valid_sources[0x41]	64655	1			T5	143		T116	70		T197	58
valid_sources[0x42]	77331	1			T28	1		T30	4		T33	2
valid_sources[0x43]	70054	1			T30	45		T33	2		T44	1
valid_sources[0x44]	51547	1			T33	1		T34	1		T45	1
valid_sources[0x45]	50232	1			T34	1		T35	4		T5	199
valid_sources[0x46]	98088	1			T5	172		T89	1		T116	84
valid_sources[0x47]	80632	1			T34	10		T35	7		T5	190
valid_sources[0x48]	84972	1			T33	1		T34	3		T44	2
valid_sources[0x49]	49599	1			T33	2		T44	1		T45	1
valid_sources[0x4a]	63925	1			T34	3		T44	1		T5	201
valid_sources[0x4b]	50382	1			T33	1		T90	2		T45	1
valid_sources[0x4c]	50416	1			T5	169		T116	81		T197	76
valid_sources[0x4d]	50748	1			T28	1		T30	13		T44	2
valid_sources[0x4e]	115098	1			T33	1		T44	1		T5	193
valid_sources[0x4f]	62483	1			T33	1		T44	1		T5	220
valid_sources[0x50]	65780	1			T33	1		T5	230		T116	88
valid_sources[0x51]	49160	1			T33	1		T44	1		T45	2
valid_sources[0x52]	117362	1			T44	1		T5	185		T116	78
valid_sources[0x53]	49371	1			T5	196		T116	84		T197	54
valid_sources[0x54]	51257	1			T44	1		T5	201		T116	80
valid_sources[0x55]	50358	1			T33	1		T45	1		T5	182
valid_sources[0x56]	61361	1			T33	1		T44	3		T45	3
valid_sources[0x57]	51457	1			T1	12		T44	1		T45	2
valid_sources[0x58]	72847	1			T5	246		T116	81		T197	55
valid_sources[0x59]	50408	1			T45	2		T5	171		T116	82
valid_sources[0x5a]	51362	1			T44	1		T5	143		T89	1
valid_sources[0x5b]	49826	1			T35	3		T44	1		T5	232
valid_sources[0x5c]	120300	1			T45	2		T5	186		T116	81
valid_sources[0x5d]	51127	1			T28	3		T5	211		T116	81
valid_sources[0x5e]	73534	1			T33	1		T45	5		T5	187
valid_sources[0x5f]	51381	1			T5	226		T89	1		T116	71
valid_sources[0x60]	72634	1			T33	1		T34	1		T42	3
valid_sources[0x61]	61145	1			T32	130		T33	3		T5	246
valid_sources[0x62]	51486	1			T44	2		T5	236		T89	1
valid_sources[0x63]	49540	1			T35	8		T5	220		T116	100
valid_sources[0x64]	49070	1			T33	2		T34	1		T5	248
valid_sources[0x65]	54427	1			T45	2		T5	204		T116	83
valid_sources[0x66]	69445	1			T44	2		T45	2		T5	197
valid_sources[0x67]	50820	1			T35	4		T5	223		T116	90
valid_sources[0x68]	51650	1			T45	6		T5	147		T116	69
valid_sources[0x69]	49382	1			T45	2		T5	242		T89	1
valid_sources[0x6a]	50858	1			T2	37		T33	2		T34	3
valid_sources[0x6b]	51103	1			T33	2		T34	4		T35	9
valid_sources[0x6c]	49393	1			T45	3		T5	244		T89	1
valid_sources[0x6d]	49864	1			T35	1		T90	3		T44	2
valid_sources[0x6e]	51359	1			T35	1		T45	2		T5	223
valid_sources[0x6f]	50298	1			T5	193		T89	4		T116	72
valid_sources[0x70]	50567	1			T34	4		T5	201		T89	1
valid_sources[0x71]	49275	1			T35	2		T45	5		T5	176
valid_sources[0x72]	49529	1			T34	3		T45	1		T5	219
valid_sources[0x73]	50448	1			T90	1		T44	4		T5	178
valid_sources[0x74]	62976	1			T36	11		T5	180		T116	82
valid_sources[0x75]	49113	1			T30	22		T5	243		T116	83
valid_sources[0x76]	64464	1			T34	4		T45	4		T5	260
valid_sources[0x77]	49409	1			T44	1		T5	191		T116	85
valid_sources[0x78]	49211	1			T34	3		T5	220		T116	88
valid_sources[0x79]	73909	1			T45	4		T42	1		T5	195
valid_sources[0x7a]	51124	1			T28	1		T5	239		T116	67
valid_sources[0x7b]	50874	1			T33	1		T34	4		T45	1
valid_sources[0x7c]	51098	1			T5	267		T116	77		T197	64
valid_sources[0x7d]	50641	1			T35	1		T45	2		T5	186
valid_sources[0x7e]	50094	1			T33	1		T35	3		T44	1
valid_sources[0x7f]	60767	1			T33	2		T35	2		T44	1
valid_sources[0x80]	50377	1			T28	2		T5	257		T116	84

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8504847

1

T1

1

T2

4

T3

20787

values[0x0]

all_enables

biggest_size

260426

1

T1

2

T2

7

T3

50

values[0x1]

all_enables

biggest_size

242840

1

T1

2

T2

8

T3

44