Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

8410972

1

T1

7

T2

18

T3

21005

full_word

9009323

1

T1

5

T2

19

T3

20881

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	17419985	1			T1	12		T2	37		T3	41886
auto[TlIntgErrCmd]	110	1			T275	5		T277	9		T278	4
auto[TlIntgErrData]	92	1			T275	4		T277	6		T278	8
auto[TlIntgErrBoth]	108	1			T275	11		T277	5		T278	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16777708

1

T1

3

T2

15

T3

41743

auto[1]

642587

1

T1

9

T2

22

T3

143

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8272492	1			T1	2		T2	11		T3	20956
auto[TlIntgErrNone]	partial	auto[1]	138207	1			T1	5		T2	7		T3	49
auto[TlIntgErrNone]	full_word	auto[0]	8505081	1			T1	1		T2	4		T3	20787
auto[TlIntgErrNone]	full_word	auto[1]	504205	1			T1	4		T2	15		T3	94
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T275	3		T278	2		T290	6
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T275	2		T277	5		T278	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T277	2		T293	1		T509	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T277	2		T510	1		T513	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T275	3		T277	3		T278	5
auto[TlIntgErrData]	partial	auto[1]	39	1			T275	1		T277	3		T278	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T514	1		T515	1		T516	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T293	2		T517	1		T518	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T275	2		T277	3		T278	2
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T275	8		T277	1		T278	5
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T275	1		T277	1		T519	2
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T278	1		T290	1		T509	1