Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	571227805	13979	0	0
ep_in_enable_rd_A	571227805	3002	0	0
ep_out_enable_rd_A	571227805	3226	0	0
in_iso_rd_A	571227805	2991	0	0
intr_enable_rd_A	571227805	4272	0	0
out_iso_rd_A	571227805	3273	0	0
phy_config_rd_A	571227805	2018	0	0
phy_pins_drive_rd_A	571227805	2591	0	0
rxenable_setup_rd_A	571227805	2895	0	0
set_nak_out_rd_A	571227805	3067	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	13979	0	0
T224	13947	603	0	0
T225	12494	867	0	0
T226	10446	803	0	0
T275	25626	3	0	0
T277	36231	4	0	0
T278	36151	2	0	0
T283	5900	733	0	0
T289	3043	410	0	0
T290	36121	2	0	0
T291	5368	14	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	3002	0	0
T224	13947	8	0	0
T270	4452	36	0	0
T292	11224	46	0	0
T302	10183	97	0	0
T317	9530	28	0	0
T319	13637	50	0	0
T325	52265	282	0	0
T326	17160	95	0	0
T327	2947	1	0	0
T328	8770	21	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	3226	0	0
T270	4452	15	0	0
T292	11224	74	0	0
T302	10183	108	0	0
T317	9530	40	0	0
T319	13637	30	0	0
T325	52265	236	0	0
T326	17160	124	0	0
T328	8770	25	0	0
T329	3589	4	0	0
T330	4938	20	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	2991	0	0
T270	4452	2	0	0
T292	11224	14	0	0
T302	10183	108	0	0
T317	9530	19	0	0
T319	13637	49	0	0
T325	52265	201	0	0
T326	17160	157	0	0
T327	2947	6	0	0
T328	8770	3	0	0
T329	3589	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	4272	0	0
T233	2283	4	0	0
T270	4452	37	0	0
T302	10183	139	0	0
T317	9530	42	0	0
T319	13637	46	0	0
T325	52265	204	0	0
T326	17160	100	0	0
T331	2409	12	0	0
T332	4771	1	0	0
T333	2459	7	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	3273	0	0
T292	11224	63	0	0
T302	10183	89	0	0
T317	9530	5	0	0
T319	13637	50	0	0
T325	52265	226	0	0
T326	17160	87	0	0
T327	2947	47	0	0
T328	8770	10	0	0
T329	3589	4	0	0
T330	4938	7	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	2018	0	0
T270	4452	32	0	0
T292	11224	25	0	0
T302	10183	78	0	0
T317	9530	27	0	0
T319	13637	69	0	0
T325	52265	194	0	0
T326	17160	101	0	0
T327	2947	16	0	0
T328	8770	4	0	0
T329	3589	7	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	2591	0	0
T270	4452	2	0	0
T292	11224	13	0	0
T302	10183	62	0	0
T317	9530	45	0	0
T319	13637	43	0	0
T325	52265	215	0	0
T326	17160	108	0	0
T327	2947	24	0	0
T328	8770	36	0	0
T329	3589	1	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	2895	0	0
T270	4452	28	0	0
T292	11224	60	0	0
T302	10183	88	0	0
T317	9530	16	0	0
T319	13637	95	0	0
T325	52265	226	0	0
T326	17160	80	0	0
T327	2947	7	0	0
T328	8770	17	0	0
T329	3589	4	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	3067	0	0
T270	4452	23	0	0
T292	11224	101	0	0
T302	10183	114	0	0
T317	9530	36	0	0
T319	13637	47	0	0
T325	52265	215	0	0
T326	17160	116	0	0
T327	2947	66	0	0
T328	8770	47	0	0
T329	3589	1	0	0