Unified Coverage Report :: Module Instance :: tb.dut.usbdev_avsetupfifo

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	96.77			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	96.77			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	98.59	88.57			96.00	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	98.59	88.57			96.00	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	98.59	88.57			96.00	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T29

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T62,T63
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T3,T29

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T29
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T29,T32

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T29
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	569504669	125196164	0	0
DepthKnown_A	569504669	569221281	0	0
RvalidKnown_A	569504669	569221281	0	0
WreadyKnown_A	569504669	569221281	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	569504669	125196164	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	125196164	0	0
T2	14773	8646	0	0
T3	285206	278385	0	0
T4	168123	160538	0	0
T5	0	107727	0	0
T26	478591	0	0	0
T27	11954	0	0	0
T28	8847	0	0	0
T29	141829	125079	0	0
T30	35640	0	0	0
T31	10545	0	0	0
T32	0	1693	0	0
T33	0	1684	0	0
T36	7417	0	0	0
T44	0	1696	0	0
T89	0	1710	0	0
T91	0	1683	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	569221281	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	569221281	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	569221281	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	125196164	0	0
T2	14773	8646	0	0
T3	285206	278385	0	0
T4	168123	160538	0	0
T5	0	107727	0	0
T26	478591	0	0	0
T27	11954	0	0	0
T28	8847	0	0	0
T29	141829	125079	0	0
T30	35640	0	0	0
T31	10545	0	0	0
T32	0	1693	0	0
T33	0	1684	0	0
T36	7417	0	0	0
T44	0	1696	0	0
T89	0	1710	0	0
T91	0	1683	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T64,T92,T93
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T26,T27

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	569504669	273794571	0	0
DepthKnown_A	569504669	569221281	0	0
RvalidKnown_A	569504669	569221281	0	0
WreadyKnown_A	569504669	569221281	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	569504669	273794571	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	273794571	0	0
T1	6880	1249	0	0
T2	14773	2005	0	0
T3	285206	278369	0	0
T26	478591	399	0	0
T27	11954	2369	0	0
T28	8847	1340	0	0
T29	141829	134478	0	0
T30	35640	12626	0	0
T31	10545	2909	0	0
T36	7417	847	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	569221281	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	569221281	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	569221281	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	273794571	0	0
T1	6880	1249	0	0
T2	14773	2005	0	0
T3	285206	278369	0	0
T26	478591	399	0	0
T27	11954	2369	0	0
T28	8847	1340	0	0
T29	141829	134478	0	0
T30	35640	12626	0	0
T31	10545	2909	0	0
T36	7417	847	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T47,T48,T49
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T3,T26,T27

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T26,T27

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T3,T26,T27
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T26,T27

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T26,T27
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T26,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T26,T27
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	569504669	40780776	0	0
DepthKnown_A	569504669	569221281	0	0
RvalidKnown_A	569504669	569221281	0	0
WreadyKnown_A	569504669	569221281	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	569504669	40780776	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	40780776	0	0
T3	285206	245	0	0
T4	168123	1455	0	0
T26	478591	108	0	0
T27	11954	91	0	0
T28	8847	94	0	0
T29	141829	716649	0	0
T30	35640	1117	0	0
T31	10545	0	0	0
T32	26296	591	0	0
T33	0	614	0	0
T34	0	649	0	0
T36	7417	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	569221281	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	569221281	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	569221281	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	40780776	0	0
T3	285206	245	0	0
T4	168123	1455	0	0
T26	478591	108	0	0
T27	11954	91	0	0
T28	8847	94	0	0
T29	141829	716649	0	0
T30	35640	1117	0	0
T31	10545	0	0	0
T32	26296	591	0	0
T33	0	614	0	0
T34	0	649	0	0
T36	7417	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	571227805	17693272	0	0
DepthKnown_A	571227805	570904660	0	0
RvalidKnown_A	571227805	570904660	0	0
WreadyKnown_A	571227805	570904660	0	0
gen_passthru_fifo.paramCheckPass	3739	3739	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	17693272	0	0
T1	6880	12	0	0
T2	14773	37	0	0
T3	285206	41886	0	0
T26	478591	26	0	0
T27	11954	28	0	0
T28	8847	30	0	0
T29	141829	2801	0	0
T30	35640	199	0	0
T31	10545	10	0	0
T36	7417	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	570904660	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	570904660	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	570904660	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3739	3739	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T36	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	571227805	26168437	0	0
DepthKnown_A	571227805	570904660	0	0
RvalidKnown_A	571227805	570904660	0	0
WreadyKnown_A	571227805	570904660	0	0
gen_passthru_fifo.paramCheckPass	3739	3739	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	26168437	0	0
T1	6880	12	0	0
T2	14773	212	0	0
T3	285206	41886	0	0
T26	478591	26	0	0
T27	11954	28	0	0
T28	8847	30	0	0
T29	141829	2801	0	0
T30	35640	929	0	0
T31	10545	10	0	0
T36	7417	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	570904660	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	570904660	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	570904660	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3739	3739	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T36	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	571227805	941853	0	0
DepthKnown_A	571227805	570904660	0	0
RvalidKnown_A	571227805	570904660	0	0
WreadyKnown_A	571227805	570904660	0	0
gen_passthru_fifo.paramCheckPass	3739	3739	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	941853	0	0
T2	14773	4	0	0
T3	285206	0	0	0
T4	168123	0	0	0
T26	478591	0	0	0
T27	11954	16	0	0
T28	8847	8	0	0
T29	141829	498	0	0
T30	35640	72	0	0
T31	10545	0	0	0
T32	0	71	0	0
T33	0	53	0	0
T34	0	96	0	0
T35	0	63	0	0
T36	7417	0	0	0
T90	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	570904660	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	570904660	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	570904660	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3739	3739	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T36	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	571227805	1768503	0	0
DepthKnown_A	571227805	570904660	0	0
RvalidKnown_A	571227805	570904660	0	0
WreadyKnown_A	571227805	570904660	0	0
gen_passthru_fifo.paramCheckPass	3739	3739	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	1768503	0	0
T2	14773	20	0	0
T3	285206	0	0	0
T4	168123	0	0	0
T26	478591	0	0	0
T27	11954	16	0	0
T28	8847	8	0	0
T29	141829	498	0	0
T30	35640	344	0	0
T31	10545	0	0	0
T32	0	71	0	0
T33	0	53	0	0
T34	0	96	0	0
T35	0	63	0	0
T36	7417	0	0	0
T90	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	570904660	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	570904660	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	570904660	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3739	3739	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T36	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	571227805	16683593	0	0
DepthKnown_A	571227805	570904660	0	0
RvalidKnown_A	571227805	570904660	0	0
WreadyKnown_A	571227805	570904660	0	0
gen_passthru_fifo.paramCheckPass	3739	3739	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	16683593	0	0
T1	6880	12	0	0
T2	14773	33	0	0
T3	285206	41886	0	0
T26	478591	26	0	0
T27	11954	12	0	0
T28	8847	22	0	0
T29	141829	2303	0	0
T30	35640	127	0	0
T31	10545	10	0	0
T36	7417	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	570904660	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	570904660	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	570904660	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3739	3739	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T36	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	571227805	24399934	0	0
DepthKnown_A	571227805	570904660	0	0
RvalidKnown_A	571227805	570904660	0	0
WreadyKnown_A	571227805	570904660	0	0
gen_passthru_fifo.paramCheckPass	3739	3739	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	24399934	0	0
T1	6880	12	0	0
T2	14773	192	0	0
T3	285206	41886	0	0
T26	478591	26	0	0
T27	11954	12	0	0
T28	8847	22	0	0
T29	141829	2303	0	0
T30	35640	585	0	0
T31	10545	10	0	0
T36	7417	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	570904660	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	570904660	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	571227805	570904660	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3739	3739	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T36	1	1	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T27,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T27,T28

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T27,T28

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T2,T28,T29
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T27,T28

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T27,T28
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T27,T28

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T27,T28
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	569504669	1710096	0	0
DepthKnown_A	569504669	569221281	0	0
RvalidKnown_A	569504669	569221281	0	0
WreadyKnown_A	569504669	569221281	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	569504669	1710096	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	1710096	0	0
T2	14773	20	0	0
T3	285206	0	0	0
T4	168123	0	0	0
T26	478591	0	0	0
T27	11954	16	0	0
T28	8847	8	0	0
T29	141829	498	0	0
T30	35640	344	0	0
T31	10545	0	0	0
T32	0	71	0	0
T33	0	53	0	0
T34	0	96	0	0
T35	0	63	0	0
T36	7417	0	0	0
T90	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	569221281	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	569221281	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	569221281	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	1710096	0	0
T2	14773	20	0	0
T3	285206	0	0	0
T4	168123	0	0	0
T26	478591	0	0	0
T27	11954	16	0	0
T28	8847	8	0	0
T29	141829	498	0	0
T30	35640	344	0	0
T31	10545	0	0	0
T32	0	71	0	0
T33	0	53	0	0
T34	0	96	0	0
T35	0	63	0	0
T36	7417	0	0	0
T90	0	16	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T27,T28,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T27,T28,T29

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T27,T28,T29

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T27,T28,T29

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T27,T28,T29
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T27,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T29
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	569504669	612183	0	0
DepthKnown_A	569504669	569221281	0	0
RvalidKnown_A	569504669	569221281	0	0
WreadyKnown_A	569504669	569221281	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	569504669	612183	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	612183	0	0
T4	168123	0	0	0
T27	11954	16	0	0
T28	8847	8	0	0
T29	141829	82	0	0
T30	35640	72	0	0
T31	10545	0	0	0
T32	26296	52	0	0
T33	25040	35	0	0
T34	25575	96	0	0
T35	0	63	0	0
T36	7417	0	0	0
T44	0	24	0	0
T90	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	569221281	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	569221281	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	569221281	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	612183	0	0
T4	168123	0	0	0
T27	11954	16	0	0
T28	8847	8	0	0
T29	141829	82	0	0
T30	35640	72	0	0
T31	10545	0	0	0
T32	26296	52	0	0
T33	25040	35	0	0
T34	25575	96	0	0
T35	0	63	0	0
T36	7417	0	0	0
T44	0	24	0	0
T90	0	16	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	18	18	100.00
Logical	18	18	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T30,T45,T89
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T27,T28,T29

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T27,T28,T29

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T28,T29,T30
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T27,T28,T29

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T28,T29

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T27,T28,T29

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T30,T45,T89
1	0	Covered	T27,T28,T29
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T27,T28,T29
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T29
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T27,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T29
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	569504669	1166619	0	0
DepthKnown_A	569504669	569221281	0	0
RvalidKnown_A	569504669	569221281	0	0
WreadyKnown_A	569504669	569221281	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	569504669	1166619	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	1166619	0	0
T4	168123	0	0	0
T27	11954	16	0	0
T28	8847	8	0	0
T29	141829	82	0	0
T30	35640	344	0	0
T31	10545	0	0	0
T32	26296	52	0	0
T33	25040	35	0	0
T34	25575	96	0	0
T35	0	63	0	0
T36	7417	0	0	0
T44	0	24	0	0
T90	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	569221281	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	569221281	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	569221281	0	0
T1	6880	6790	0	0
T2	14773	14708	0	0
T3	285206	285130	0	0
T26	478591	478528	0	0
T27	11954	11857	0	0
T28	8847	8789	0	0
T29	141829	141821	0	0
T30	35640	35555	0	0
T31	10545	10492	0	0
T36	7417	7362	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	569504669	1166619	0	0
T4	168123	0	0	0
T27	11954	16	0	0
T28	8847	8	0	0
T29	141829	82	0	0
T30	35640	344	0	0
T31	10545	0	0	0
T32	26296	52	0	0
T33	25040	35	0	0
T34	25575	96	0	0
T35	0	63	0	0
T36	7417	0	0	0
T44	0	24	0	0
T90	0	16	0	0