Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9184486	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9796420

1

T1

303

T2

6

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	18346978	1			T1	325		T2	2		T3	36
values[0x0]	316268	1			T1	10		T2	3		T3	14
values[0x1]	317660	1			T1	14		T2	6		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7300406	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

11680500

1

T1

311

T2

7

T3

27

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	80109	1			T27	6		T28	15		T7	4
valid_sources[0x01]	55451	1			T27	4		T28	30		T7	1
valid_sources[0x02]	79878	1			T27	27		T28	18		T7	1
valid_sources[0x03]	114937	1			T27	205		T28	40		T7	2
valid_sources[0x04]	71606	1			T28	25		T7	5		T8	1
valid_sources[0x05]	146914	1			T27	22		T28	28		T7	1
valid_sources[0x06]	59396	1			T27	59		T28	38		T8	1
valid_sources[0x07]	56874	1			T27	4		T28	25		T7	3
valid_sources[0x08]	55731	1			T27	5		T28	28		T20	29
valid_sources[0x09]	158084	1			T27	1		T28	33		T20	31
valid_sources[0x0a]	87450	1			T27	6		T28	24		T7	2
valid_sources[0x0b]	65330	1			T27	10		T28	26		T7	3
valid_sources[0x0c]	143985	1			T31	1		T27	1		T28	37
valid_sources[0x0d]	68277	1			T27	2		T28	26		T8	1
valid_sources[0x0e]	56642	1			T31	3		T27	27		T28	45
valid_sources[0x0f]	55529	1			T27	1		T28	15		T7	1
valid_sources[0x10]	72516	1			T27	4		T28	65		T7	1
valid_sources[0x11]	54820	1			T27	2		T28	26		T7	1
valid_sources[0x12]	54943	1			T27	11		T28	25		T20	41
valid_sources[0x13]	55776	1			T2	1		T27	26		T28	18
valid_sources[0x14]	56351	1			T27	47		T28	22		T7	1
valid_sources[0x15]	88285	1			T31	1		T27	27		T28	25
valid_sources[0x16]	56412	1			T27	2		T28	34		T7	1
valid_sources[0x17]	55481	1			T31	2		T27	12		T28	21
valid_sources[0x18]	55513	1			T31	1		T27	13		T28	24
valid_sources[0x19]	56747	1			T31	1		T27	18		T28	27
valid_sources[0x1a]	57335	1			T27	3		T28	51		T20	41
valid_sources[0x1b]	56829	1			T27	1		T28	30		T7	1
valid_sources[0x1c]	56496	1			T27	4		T28	33		T7	3
valid_sources[0x1d]	66206	1			T27	9		T28	30		T7	1
valid_sources[0x1e]	56273	1			T27	2		T28	43		T20	34
valid_sources[0x1f]	55898	1			T27	4		T28	8		T20	24
valid_sources[0x20]	154135	1			T31	1		T28	28		T8	1
valid_sources[0x21]	63494	1			T27	4		T28	9		T20	27
valid_sources[0x22]	55885	1			T28	37		T32	7		T7	1
valid_sources[0x23]	54617	1			T27	19		T28	22		T30	149
valid_sources[0x24]	54892	1			T27	39		T28	24		T7	2
valid_sources[0x25]	201262	1			T27	2		T28	41		T32	14
valid_sources[0x26]	56002	1			T27	83		T28	28		T7	2
valid_sources[0x27]	54374	1			T27	5		T28	64		T7	1
valid_sources[0x28]	56338	1			T27	161		T28	45		T7	1
valid_sources[0x29]	56177	1			T27	60		T28	38		T7	3
valid_sources[0x2a]	57455	1			T28	35		T20	25		T6	39
valid_sources[0x2b]	67533	1			T27	68		T28	17		T7	3
valid_sources[0x2c]	57130	1			T27	64		T28	36		T7	2
valid_sources[0x2d]	122353	1			T27	2		T28	30		T7	6
valid_sources[0x2e]	56296	1			T27	1		T28	15		T7	1
valid_sources[0x2f]	120384	1			T27	7		T28	38		T7	2
valid_sources[0x30]	55001	1			T27	4		T28	22		T7	1
valid_sources[0x31]	55166	1			T2	1		T27	6		T28	18
valid_sources[0x32]	54498	1			T27	3		T28	35		T8	1
valid_sources[0x33]	55340	1			T27	3		T28	34		T32	6
valid_sources[0x34]	94672	1			T27	23		T28	36		T7	2
valid_sources[0x35]	55449	1			T27	1		T28	46		T7	1
valid_sources[0x36]	71769	1			T31	2		T27	2		T28	18
valid_sources[0x37]	54547	1			T31	2		T28	28		T7	2
valid_sources[0x38]	55242	1			T27	3		T28	27		T32	14
valid_sources[0x39]	84701	1			T28	32		T20	39		T6	35
valid_sources[0x3a]	55350	1			T27	2		T28	43		T7	1
valid_sources[0x3b]	55763	1			T28	45		T7	1		T19	7
valid_sources[0x3c]	125450	1			T27	4		T28	25		T20	47
valid_sources[0x3d]	57548	1			T27	13		T28	19		T7	2
valid_sources[0x3e]	55296	1			T27	2		T28	36		T7	2
valid_sources[0x3f]	65264	1			T27	83		T28	19		T20	28
valid_sources[0x40]	55269	1			T27	1		T28	36		T7	1
valid_sources[0x41]	53945	1			T27	6		T28	16		T7	2
valid_sources[0x42]	141388	1			T27	10		T28	14		T7	1
valid_sources[0x43]	144586	1			T27	1		T28	43		T7	1
valid_sources[0x44]	54158	1			T27	32		T28	23		T7	2
valid_sources[0x45]	56097	1			T31	2		T27	120		T28	36
valid_sources[0x46]	55927	1			T27	40		T28	37		T7	2
valid_sources[0x47]	93556	1			T27	1		T28	8		T7	1
valid_sources[0x48]	55802	1			T27	23		T28	38		T32	34
valid_sources[0x49]	68142	1			T27	52		T28	17		T7	1
valid_sources[0x4a]	98136	1			T27	25		T28	47		T7	2
valid_sources[0x4b]	55676	1			T28	13		T7	1		T20	18
valid_sources[0x4c]	56147	1			T27	24		T28	32		T7	3
valid_sources[0x4d]	68958	1			T27	20		T28	39		T20	14
valid_sources[0x4e]	97965	1			T27	8		T28	22		T7	1
valid_sources[0x4f]	56611	1			T27	4		T28	24		T7	2
valid_sources[0x50]	56317	1			T27	1		T28	25		T7	3
valid_sources[0x51]	116722	1			T27	29		T28	44		T7	2
valid_sources[0x52]	54558	1			T27	103		T28	24		T7	1
valid_sources[0x53]	76722	1			T27	59		T28	20		T8	3
valid_sources[0x54]	56597	1			T27	34		T28	36		T7	1
valid_sources[0x55]	55590	1			T27	1		T28	30		T7	2
valid_sources[0x56]	98952	1			T27	14		T28	45		T7	1
valid_sources[0x57]	156315	1			T2	1		T27	54		T28	8
valid_sources[0x58]	57451	1			T27	34		T28	31		T7	1
valid_sources[0x59]	55836	1			T27	29		T28	27		T32	7
valid_sources[0x5a]	89331	1			T27	4		T28	23		T32	13
valid_sources[0x5b]	72569	1			T3	9		T28	18		T7	4
valid_sources[0x5c]	82908	1			T27	3		T28	28		T7	2
valid_sources[0x5d]	57322	1			T27	3		T28	23		T7	1
valid_sources[0x5e]	55908	1			T27	15		T28	13		T32	9
valid_sources[0x5f]	55478	1			T27	2		T28	20		T20	34
valid_sources[0x60]	76447	1			T27	163		T28	19		T7	1
valid_sources[0x61]	57001	1			T27	22		T28	18		T7	2
valid_sources[0x62]	62643	1			T31	2		T27	7		T28	18
valid_sources[0x63]	56547	1			T27	37		T28	30		T7	1
valid_sources[0x64]	122216	1			T27	18		T28	20		T20	22
valid_sources[0x65]	56376	1			T28	26		T7	5		T20	29
valid_sources[0x66]	71656	1			T3	10		T27	10		T28	24
valid_sources[0x67]	128983	1			T31	3		T27	112		T28	19
valid_sources[0x68]	65514	1			T28	14		T7	1		T20	40
valid_sources[0x69]	144171	1			T27	4		T28	27		T32	8
valid_sources[0x6a]	56089	1			T28	27		T7	2		T20	21
valid_sources[0x6b]	55933	1			T27	7		T28	25		T7	3
valid_sources[0x6c]	63527	1			T27	28		T28	43		T7	2
valid_sources[0x6d]	56364	1			T27	8		T28	45		T7	2
valid_sources[0x6e]	53714	1			T28	24		T8	1		T20	14
valid_sources[0x6f]	158855	1			T27	64		T28	33		T7	2
valid_sources[0x70]	56448	1			T27	109		T28	37		T7	3
valid_sources[0x71]	78996	1			T27	91		T28	33		T7	3
valid_sources[0x72]	67463	1			T27	3		T28	28		T20	16
valid_sources[0x73]	78016	1			T27	66		T28	24		T7	1
valid_sources[0x74]	70820	1			T27	30		T28	15		T7	1
valid_sources[0x75]	207957	1			T27	3		T28	37		T7	1
valid_sources[0x76]	77964	1			T27	4		T28	39		T32	81
valid_sources[0x77]	55537	1			T27	4		T28	27		T7	1
valid_sources[0x78]	66186	1			T28	27		T7	1		T8	1
valid_sources[0x79]	56983	1			T27	48		T28	17		T7	2
valid_sources[0x7a]	59741	1			T28	22		T7	1		T8	2
valid_sources[0x7b]	55295	1			T27	38		T28	23		T20	36
valid_sources[0x7c]	73206	1			T27	74		T28	32		T7	1
valid_sources[0x7d]	57170	1			T27	2		T28	20		T7	3
valid_sources[0x7e]	55490	1			T27	12		T28	32		T7	1
valid_sources[0x7f]	55073	1			T2	1		T27	2		T28	18
valid_sources[0x80]	56280	1			T27	9		T28	30		T20	37

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9284786

1

T1

297

T2

1

T3

3

values[0x0]

all_enables

biggest_size

264461

1

T1

4

T2

2

T3

9

values[0x1]

all_enables

biggest_size

247173

1

T1

2

T2

3

T3

6