Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

9199770

1

T1

46

T2

5

T3

43

full_word

9797485

1

T1

303

T2

6

T3

18

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	18996985	1			T1	349		T2	11		T3	61
auto[TlIntgErrCmd]	91	1			T266	6		T275	6		T276	6
auto[TlIntgErrData]	83	1			T266	8		T275	7		T276	3
auto[TlIntgErrBoth]	96	1			T266	6		T275	7		T276	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18349003

1

T1

325

T2

2

T3

36

auto[1]

648252

1

T1

24

T2

9

T3

25

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9063913	1			T1	28		T2	1		T3	33
auto[TlIntgErrNone]	partial	auto[1]	135612	1			T1	18		T2	4		T3	10
auto[TlIntgErrNone]	full_word	auto[0]	9284978	1			T1	297		T2	1		T3	3
auto[TlIntgErrNone]	full_word	auto[1]	512482	1			T1	6		T2	5		T3	15
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T266	1		T275	3		T276	3
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T266	5		T275	3		T276	3
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T344	1		T345	1		T346	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T266	6		T275	4		T276	2
auto[TlIntgErrData]	partial	auto[1]	35	1			T266	2		T275	2		T276	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T347	1		T348	1		T349	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T275	1		T344	1		T350	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T266	4		T275	1		T276	4
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T266	2		T275	5		T276	7
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T351	1		T352	2		T353	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T275	1		T345	2		T354	3