Module Definition
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Module : usbdev_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.usbdev_csr_assert 100.00 100.00



Module Instance : tb.dut.usbdev_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.15 97.53 93.65 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : usbdev_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 10 10 100.00 10 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 10 10 100.00 10 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
TlulOOBAddrErr_A 581267081 12216 0 0
ep_in_enable_rd_A 581267081 3988 0 0
ep_out_enable_rd_A 581267081 3814 0 0
in_iso_rd_A 581267081 4044 0 0
intr_enable_rd_A 581267081 5594 0 0
out_iso_rd_A 581267081 4034 0 0
phy_config_rd_A 581267081 2387 0 0
phy_pins_drive_rd_A 581267081 2975 0 0
rxenable_setup_rd_A 581267081 4300 0 0
set_nak_out_rd_A 581267081 3637 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 581267081 12216 0 0
T227 8156 16 0 0
T228 6790 21 0 0
T229 4304 7 0 0
T265 3348 422 0 0
T266 57394 2 0 0
T267 12313 897 0 0
T275 67476 5 0 0
T277 5027 860 0 0
T280 6761 242 0 0
T287 4997 9 0 0

ep_in_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 581267081 3988 0 0
T229 4304 41 0 0
T270 13788 50 0 0
T275 67476 299 0 0
T276 46552 439 0 0
T287 4997 7 0 0
T298 4007 83 0 0
T317 12694 28 0 0
T318 8412 3 0 0
T319 6778 25 0 0
T320 5550 2 0 0

ep_out_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 581267081 3814 0 0
T229 4304 55 0 0
T270 13788 44 0 0
T275 67476 88 0 0
T276 46552 527 0 0
T287 4997 2 0 0
T298 4007 42 0 0
T317 12694 33 0 0
T318 8412 30 0 0
T319 6778 25 0 0
T320 5550 31 0 0

in_iso_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 581267081 4044 0 0
T229 4304 62 0 0
T270 13788 47 0 0
T275 67476 263 0 0
T280 6761 5 0 0
T287 4997 4 0 0
T298 4007 38 0 0
T317 12694 9 0 0
T318 8412 5 0 0
T319 6778 17 0 0
T320 5550 5 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 581267081 5594 0 0
T229 4304 11 0 0
T232 2146 7 0 0
T270 13788 29 0 0
T275 67476 353 0 0
T287 4997 40 0 0
T298 4007 150 0 0
T317 12694 60 0 0
T318 8412 13 0 0
T321 5504 12 0 0
T322 3138 21 0 0

out_iso_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 581267081 4034 0 0
T229 4304 51 0 0
T270 13788 73 0 0
T275 67476 309 0 0
T276 46552 482 0 0
T287 4997 6 0 0
T298 4007 31 0 0
T317 12694 74 0 0
T318 8412 5 0 0
T319 6778 13 0 0
T320 5550 4 0 0

phy_config_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 581267081 2387 0 0
T229 4304 33 0 0
T270 13788 42 0 0
T275 67476 149 0 0
T276 46552 194 0 0
T287 4997 23 0 0
T304 39963 191 0 0
T317 12694 30 0 0
T318 8412 9 0 0
T319 6778 19 0 0
T320 5550 21 0 0

phy_pins_drive_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 581267081 2975 0 0
T229 4304 12 0 0
T270 13788 15 0 0
T275 67476 141 0 0
T276 46552 337 0 0
T287 4997 18 0 0
T298 4007 8 0 0
T317 12694 46 0 0
T318 8412 43 0 0
T319 6778 19 0 0
T320 5550 4 0 0

rxenable_setup_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 581267081 4300 0 0
T229 4304 60 0 0
T270 13788 54 0 0
T275 67476 278 0 0
T276 46552 509 0 0
T287 4997 8 0 0
T298 4007 94 0 0
T317 12694 55 0 0
T318 8412 53 0 0
T319 6778 17 0 0
T320 5550 43 0 0

set_nak_out_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 581267081 3637 0 0
T229 4304 6 0 0
T270 13788 26 0 0
T275 67476 216 0 0
T276 46552 422 0 0
T287 4997 34 0 0
T298 4007 97 0 0
T317 12694 55 0 0
T318 8412 37 0 0
T319 6778 9 0 0
T320 5550 7 0 0