Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : usb_fs_nb_out_pe
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.37 96.85 92.54 100.00 92.45 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe 96.72 96.85 92.54 100.00 94.23 100.00



Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.72 96.85 92.54 100.00 94.23 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.72 96.85 92.54 100.00 94.23 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_usb_fs_nb_pe


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : usb_fs_nb_out_pe
Line No.TotalCoveredPercent
TOTAL12712396.85
CONT_ASSIGN9011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN17811100.00
ALWAYS18466100.00
ALWAYS19644100.00
ALWAYS212555192.73
CONT_ASSIGN32611100.00
ALWAYS32933100.00
ALWAYS33733100.00
ALWAYS34677100.00
CONT_ASSIGN36011100.00
ALWAYS36355100.00
ALWAYS37399100.00
ALWAYS39033100.00
ALWAYS40266100.00
CONT_ASSIGN41811100.00
ALWAYS42166100.00
CONT_ASSIGN43511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
90 1 1
131 1 1
132 1 1
134 1 1
140 1 1
144 1 1
148 1 1
152 1 1
157 1 1
163 1 1
164 1 1
171 1 1
172 1 1
175 1 1
176 1 1
178 1 1
184 1 1
185 1 1
187 1 1
188 1 1
189 1 1
190 1 1
MISSING_ELSE
196 1 1
197 1 1
199 1 1
200 1 1
MISSING_ELSE
212 1 1
213 1 1
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
221 1 1
225 1 1
226 1 1
227 1 1
229 1 1
237 1 1
239 1 1
240 1 1
241 1 1
242 0 1
244 1 1
249 1 1
253 1 1
254 1 1
257 1 1
258 1 1
259 1 1
260 1 1
261 1 1
263 1 1
264 1 1
265 1 1
266 1 1
268 1 1
273 1 1
274 1 1
276 1 1
278 1 1
280 0 1
281 0 1
283 1 1
284 1 1
285 1 1
289 1 1
290 1 1
291 1 1
292 1 1
293 1 1
294 1 1
296 1 1
297 1 1
298 1 1
305 1 1
307 1 1
309 0 1
312 1 1
313 1 1
326 1 1
329 1 1
330 1 1
332 1 1
337 1 1
338 1 1
340 1 1
346 1 1
348 1 1
349 1 1
350 1 1
351 1 1
MISSING_ELSE
354 1 1
355 1 1
MISSING_ELSE
360 1 1
363 1 1
364 1 1
365 1 1
366 1 1
368 1 1
373 1 1
374 1 1
375 1 1
376 1 1
378 1 1
379 1 1
380 1 1
381 1 1
383 1 1
390 1 1
391 1 1
393 1 1
402 1 1
403 1 1
405 1 1
406 1 1
407 1 1
408 1 1
MISSING_ELSE
418 1 1
421 1 1
422 1 1
424 1 1
425 1 1
426 1 1
427 1 1
MISSING_ELSE
435 1 1


Cond Coverage for Module : usb_fs_nb_out_pe
TotalCoveredPercent
Conditions13412492.54
Logical13412492.54
Non-Logical00
Event00

 LINE       134
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid_type == UsbPidTypeToken) && (rx_addr_i == dev_addr_i))
             ------1-----    -------2------    ----------------3---------------    ------------4------------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T31
1011CoveredT19,T69,T70
1101CoveredT1,T2,T27
1110CoveredT3,T31,T28
1111CoveredT1,T2,T31

 LINE       134
 SUB-EXPRESSION (rx_pid_type == UsbPidTypeToken)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       134
 SUB-EXPRESSION (rx_addr_i == dev_addr_i)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (token_received && (rx_pid == UsbPidOut))
             -------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T27,T28
11CoveredT1,T2,T27

 LINE       140
 SUB-EXPRESSION (rx_pid == UsbPidOut)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 EXPRESSION (token_received && (rx_pid == UsbPidSetup))
             -------1------    -----------2-----------
-1--2-StatusTests
01CoveredT3,T31,T4
10CoveredT1,T2,T31
11CoveredT4,T18,T5

 LINE       144
 SUB-EXPRESSION (rx_pid == UsbPidSetup)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T31,T4

 LINE       148
 EXPRESSION (rx_pkt_end_i && ((!rx_pkt_valid_i)))
             ------1-----    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T31,T19

 LINE       152
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)))
             ------1-----    -------2------    --------------------------3-------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT19,T68,T164
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       152
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T31
10CoveredT1,T2,T3

 LINE       152
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       152
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T31

 LINE       157
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) ))
             ------1-----    -------2------    -----------------------------3----------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T31,T19
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       157
 SUB-EXPRESSION ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) )
                    --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       157
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T31
10CoveredT1,T2,T3

 LINE       157
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       157
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T31

 LINE       164
 EXPRESSION (ep_in_hw ? rx_endp_i : '0)
             ----1---
-1-StatusTests
0CoveredT28,T20,T104
1CoveredT1,T2,T3

 LINE       175
 EXPRESSION (out_ep_enabled_i[out_ep_index_d] & ep_in_hw)
             ----------------1---------------   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT109,T107,T248
11CoveredT1,T2,T3

 LINE       178
 EXPRESSION (data_packet_received && ep_active && (rx_pid_i[3] != data_toggle_q[out_ep_index_d]))
             ----------1---------    ----2----    -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT107,T249,T172
110CoveredT1,T2,T3
111CoveredT29,T54,T61

 LINE       178
 SUB-EXPRESSION (rx_pid_i[3] != data_toggle_q[out_ep_index_d])
                -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       187
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT109,T110,T182
11CoveredT4,T18,T5

 LINE       189
 EXPRESSION (out_token_received && ep_active)
             ---------1--------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT109,T107,T200
11CoveredT1,T2,T27

 LINE       225
 EXPRESSION (ep_active && (out_token_received || (setup_token_received && ep_is_control)))
             ----1----    -------------------------------2-------------------------------
-1--2-StatusTests
01CoveredT109,T107,T200
10CoveredT1,T2,T3
11CoveredT1,T2,T27

 LINE       225
 SUB-EXPRESSION (out_token_received || (setup_token_received && ep_is_control))
                 ---------1--------    -------------------2-------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T18,T5
10CoveredT1,T2,T27

 LINE       225
 SUB-EXPRESSION (setup_token_received && ep_is_control)
                 ----------1---------    ------2------
-1--2-StatusTests
01CoveredT3,T31,T4
10CoveredT109,T250,T251
11CoveredT4,T18,T5

 LINE       241
 EXPRESSION (timeout_cntdown_q == '0)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T27
1Not Covered

 LINE       249
 EXPRESSION (((!ep_is_control)) && out_ep_iso_i[out_ep_index] && data_packet_received)
             ---------1--------    -------------2------------    ----------3---------
-1--2--3-StatusTests
011CoveredT61,T252,T253
101CoveredT1,T2,T27
110CoveredT61,T173,T254
111CoveredT61,T173,T254

 LINE       254
 EXPRESSION (bad_data_toggle && ((!out_ep_stall_i[out_ep_index])))
             -------1-------    ----------------2----------------
-1--2-StatusTests
01CoveredT1,T27,T28
10Not Covered
11CoveredT29,T54,T103

 LINE       261
 EXPRESSION (invalid_packet_received || non_data_packet_received)
             -----------1-----------    ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T27
01CoveredT82,T101
10CoveredT164,T215,T255

 LINE       278
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------
-1--2-StatusTests
00CoveredT4,T18,T5
01Not Covered
10Not Covered

 LINE       292
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------
-1--2-StatusTests
00CoveredT1,T27,T28
01Not Covered
10Not Covered

 LINE       307
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------
-1--2-StatusTests
00CoveredT61,T173,T254
01Not Covered
10Not Covered

 LINE       340
 EXPRESSION (link_reset_i ? StIdle : out_xact_state_next)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       348
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT109,T110,T182
11CoveredT4,T18,T5

 LINE       393
 EXPRESSION ((out_xact_state == StRcvdDataStart) && rx_data_put_i)
             -----------------1-----------------    ------2------
-1--2-StatusTests
01CoveredT3,T31,T19
10CoveredT1,T2,T27
11CoveredT1,T2,T27

 LINE       393
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T27

 LINE       405
 EXPRESSION ((out_xact_state == StIdle) || (out_xact_state == StRcvdOut))
             -------------1------------    --------------2--------------
-1--2-StatusTests
00CoveredT1,T2,T27
01CoveredT1,T2,T27
10CoveredT1,T2,T3

 LINE       405
 SUB-EXPRESSION (out_xact_state == StIdle)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T27
1CoveredT1,T2,T3

 LINE       405
 SUB-EXPRESSION (out_xact_state == StRcvdOut)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T27

 LINE       407
 EXPRESSION (out_ep_data_put_o && out_ep_full_i[out_ep_index])
             --------1--------    -------------2-------------
-1--2-StatusTests
01CoveredT40,T256,T109
10CoveredT1,T2,T27
11CoveredT256,T109,T150

 LINE       418
 EXPRESSION (((!nak_out_transaction)) && ((~&out_ep_put_addr_o)) && out_ep_data_put_o)
             ------------1-----------    -----------2-----------    --------3--------
-1--2--3-StatusTests
011CoveredT256,T109,T150
101CoveredT1,T27,T30
110CoveredT1,T2,T3
111CoveredT1,T2,T27

 LINE       424
 EXPRESSION (out_xact_state == StRcvdOut)
            --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T27

 LINE       426
 EXPRESSION ((out_xact_state == StRcvdDataStart) && increment_addr)
             -----------------1-----------------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T27
11CoveredT1,T2,T27

 LINE       426
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T27

 LINE       435
 EXPRESSION ((out_xact_state == StRcvdDataStart) && (ep_is_control || ((!out_ep_iso_i[out_ep_index]))) && ((!out_ep_stall_i[out_ep_index])) && bad_data_toggle)
             -----------------1-----------------    -------------------------2------------------------    ----------------3----------------    -------4-------
-1--2--3--4-StatusTests
0111CoveredT109,T110,T213
1011CoveredT61,T173,T252
1101Not Covered
1110CoveredT1,T27,T28
1111CoveredT29,T54,T103

 LINE       435
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T27

 LINE       435
 SUB-EXPRESSION (ep_is_control || ((!out_ep_iso_i[out_ep_index])))
                 ------1------    ---------------2---------------
-1--2-StatusTests
00CoveredT257,T61,T173
01CoveredT1,T2,T3
10CoveredT257,T61,T258

FSM Coverage for Module : usb_fs_nb_out_pe
Summary for FSM :: out_xact_state
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 8 8 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: out_xact_state
states   Line No.   Covered   Tests   
StIdle 340 Covered T1,T2,T3
StRcvdDataEnd 266 Covered T1,T2,T27
StRcvdDataStart 240 Covered T1,T2,T27
StRcvdIsoDataEnd 253 Covered T61,T173,T254
StRcvdOut 226 Covered T1,T2,T27


transitions   Line No.   Covered   Tests   
StIdle->StRcvdOut 226 Covered T1,T2,T27
StRcvdDataEnd->StIdle 340 Covered T1,T2,T27
StRcvdDataStart->StIdle 340 Covered T29,T54,T40
StRcvdDataStart->StRcvdDataEnd 266 Covered T1,T2,T27
StRcvdDataStart->StRcvdIsoDataEnd 253 Covered T61,T173,T254
StRcvdIsoDataEnd->StIdle 340 Covered T61,T173,T254
StRcvdOut->StIdle 340 Covered T259
StRcvdOut->StRcvdDataStart 240 Covered T1,T2,T27



Branch Coverage for Module : usb_fs_nb_out_pe
Line No.TotalCoveredPercent
Branches 53 49 92.45
TERNARY 164 2 2 100.00
IF 184 4 4 100.00
IF 196 3 3 100.00
CASE 221 18 14 77.78
IF 329 2 2 100.00
IF 337 3 3 100.00
IF 348 3 3 100.00
IF 354 2 2 100.00
IF 363 3 3 100.00
IF 373 3 3 100.00
IF 390 2 2 100.00
IF 402 4 4 100.00
IF 421 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 164 (ep_in_hw) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T28,T20,T104


LineNo. Expression -1-: 184 if ((!rst_ni)) -2-: 187 if ((setup_token_received && ep_active)) -3-: 189 if ((out_token_received && ep_active))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T4,T18,T5
0 0 1 Covered T1,T2,T27
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 196 if ((!rst_ni)) -2-: 199 if (rx_data_put_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 221 case (out_xact_state) -2-: 225 if ((ep_active && (out_token_received || (setup_token_received && ep_is_control)))) -3-: 239 if (rx_pkt_start_i) -4-: 241 if ((timeout_cntdown_q == '0)) -5-: 249 if ((((!ep_is_control) && out_ep_iso_i[out_ep_index]) && data_packet_received)) -6-: 254 if ((bad_data_toggle && (!out_ep_stall_i[out_ep_index]))) -7-: 261 if ((invalid_packet_received || non_data_packet_received)) -8-: 265 if (data_packet_received) -9-: 276 if (current_xact_setup_q) -10-: 278 if ((nak_out_transaction | out_ep_full_i[out_ep_index])) -11-: 289 if (out_ep_stall_i[out_ep_index]) -12-: 292 if ((nak_out_transaction | out_ep_full_i[out_ep_index])) -13-: 307 if ((nak_out_transaction | out_ep_full_i[out_ep_index]))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13-StatusTests
StIdle 1 - - - - - - - - - - - Covered T1,T2,T27
StIdle 0 - - - - - - - - - - - Covered T1,T2,T3
StRcvdOut - 1 - - - - - - - - - - Covered T1,T2,T27
StRcvdOut - 0 1 - - - - - - - - - Not Covered
StRcvdOut - 0 0 - - - - - - - - - Covered T1,T2,T27
StRcvdDataStart - - - 1 - - - - - - - - Covered T61,T173,T254
StRcvdDataStart - - - 0 1 - - - - - - - Covered T29,T54,T103
StRcvdDataStart - - - 0 0 1 - - - - - - Covered T164,T215,T255
StRcvdDataStart - - - 0 0 0 1 - - - - - Covered T1,T2,T27
StRcvdDataStart - - - 0 0 0 0 - - - - - Covered T1,T2,T27
StRcvdDataEnd - - - - - - - 1 1 - - - Not Covered
StRcvdDataEnd - - - - - - - 1 0 - - - Covered T4,T18,T5
StRcvdDataEnd - - - - - - - 0 - 1 - - Covered T2,T17,T23
StRcvdDataEnd - - - - - - - 0 - 0 1 - Covered T256,T109,T150
StRcvdDataEnd - - - - - - - 0 - 0 0 - Covered T1,T27,T28
StRcvdIsoDataEnd - - - - - - - - - - - 1 Not Covered
StRcvdIsoDataEnd - - - - - - - - - - - 0 Covered T61,T173,T254
default - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 329 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 337 if ((!rst_ni)) -2-: 340 (link_reset_i) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 348 if ((setup_token_received && ep_active)) -2-: 350 if (new_pkt_end)

Branches:
-1--2-StatusTests
1 - Covered T4,T18,T5
0 1 Covered T1,T27,T28
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 354 if (out_datatog_we_i)

Branches:
-1-StatusTests
1 Covered T29,T54,T103
0 Covered T1,T2,T3


LineNo. Expression -1-: 363 if ((!rst_ni)) -2-: 365 if (link_reset_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 373 if ((!rst_ni)) -2-: 378 if (out_xact_start)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T27
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 390 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 402 if ((!rst_ni)) -2-: 405 if (((out_xact_state == StIdle) || (out_xact_state == StRcvdOut))) -3-: 407 if ((out_ep_data_put_o && out_ep_full_i[out_ep_index]))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T256,T109,T150
0 0 0 Covered T1,T2,T27


LineNo. Expression -1-: 421 if ((!rst_ni)) -2-: 424 if ((out_xact_state == StRcvdOut)) -3-: 426 if (((out_xact_state == StRcvdDataStart) && increment_addr))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T27
0 0 1 Covered T1,T2,T27
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : usb_fs_nb_out_pe
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutXactStateValid_A 579551765 579266161 0 0


OutXactStateValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 579551765 579266161 0 0
T1 55430 55371 0 0
T2 10663 10595 0 0
T3 33356 33302 0 0
T4 124760 124660 0 0
T27 548958 548906 0 0
T28 144634 144626 0 0
T29 17819 17768 0 0
T30 27050 26970 0 0
T31 15434 15369 0 0
T32 12075 12003 0 0

Line Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe
Line No.TotalCoveredPercent
TOTAL12712396.85
CONT_ASSIGN9011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN17811100.00
ALWAYS18466100.00
ALWAYS19644100.00
ALWAYS212555192.73
CONT_ASSIGN32611100.00
ALWAYS32933100.00
ALWAYS33733100.00
ALWAYS34677100.00
CONT_ASSIGN36011100.00
ALWAYS36355100.00
ALWAYS37399100.00
ALWAYS39033100.00
ALWAYS40266100.00
CONT_ASSIGN41811100.00
ALWAYS42166100.00
CONT_ASSIGN43511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
90 1 1
131 1 1
132 1 1
134 1 1
140 1 1
144 1 1
148 1 1
152 1 1
157 1 1
163 1 1
164 1 1
171 1 1
172 1 1
175 1 1
176 1 1
178 1 1
184 1 1
185 1 1
187 1 1
188 1 1
189 1 1
190 1 1
MISSING_ELSE
196 1 1
197 1 1
199 1 1
200 1 1
MISSING_ELSE
212 1 1
213 1 1
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
221 1 1
225 1 1
226 1 1
227 1 1
229 1 1
237 1 1
239 1 1
240 1 1
241 1 1
242 0 1
244 1 1
249 1 1
253 1 1
254 1 1
257 1 1
258 1 1
259 1 1
260 1 1
261 1 1
263 1 1
264 1 1
265 1 1
266 1 1
268 1 1
273 1 1
274 1 1
276 1 1
278 1 1
280 0 1
281 0 1
283 1 1
284 1 1
285 1 1
289 1 1
290 1 1
291 1 1
292 1 1
293 1 1
294 1 1
296 1 1
297 1 1
298 1 1
305 1 1
307 1 1
309 0 1
312 1 1
313 1 1
Exclude Annotation: VC_COV_UNR
326 1 1
329 1 1
330 1 1
332 1 1
337 1 1
338 1 1
340 1 1
346 1 1
348 1 1
349 1 1
350 1 1
351 1 1
MISSING_ELSE
354 1 1
355 1 1
MISSING_ELSE
360 1 1
363 1 1
364 1 1
365 1 1
366 1 1
368 1 1
373 1 1
374 1 1
375 1 1
376 1 1
378 1 1
379 1 1
380 1 1
381 1 1
383 1 1
390 1 1
391 1 1
393 1 1
402 1 1
403 1 1
405 1 1
406 1 1
407 1 1
408 1 1
MISSING_ELSE
418 1 1
421 1 1
422 1 1
424 1 1
425 1 1
426 1 1
427 1 1
MISSING_ELSE
435 1 1


Cond Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe
TotalCoveredPercent
Conditions13412492.54
Logical13412492.54
Non-Logical00
Event00

 LINE       134
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid_type == UsbPidTypeToken) && (rx_addr_i == dev_addr_i))
             ------1-----    -------2------    ----------------3---------------    ------------4------------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T31
1011CoveredT19,T69,T70
1101CoveredT1,T2,T27
1110CoveredT3,T31,T28
1111CoveredT1,T2,T31

 LINE       134
 SUB-EXPRESSION (rx_pid_type == UsbPidTypeToken)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       134
 SUB-EXPRESSION (rx_addr_i == dev_addr_i)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (token_received && (rx_pid == UsbPidOut))
             -------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T27,T28
11CoveredT1,T2,T27

 LINE       140
 SUB-EXPRESSION (rx_pid == UsbPidOut)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 EXPRESSION (token_received && (rx_pid == UsbPidSetup))
             -------1------    -----------2-----------
-1--2-StatusTests
01CoveredT3,T31,T4
10CoveredT1,T2,T31
11CoveredT4,T18,T5

 LINE       144
 SUB-EXPRESSION (rx_pid == UsbPidSetup)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T31,T4

 LINE       148
 EXPRESSION (rx_pkt_end_i && ((!rx_pkt_valid_i)))
             ------1-----    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T31,T19

 LINE       152
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)))
             ------1-----    -------2------    --------------------------3-------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT19,T68,T164
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       152
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T31
10CoveredT1,T2,T3

 LINE       152
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       152
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T31

 LINE       157
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) ))
             ------1-----    -------2------    -----------------------------3----------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T31,T19
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       157
 SUB-EXPRESSION ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) )
                    --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       157
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T31
10CoveredT1,T2,T3

 LINE       157
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       157
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T31

 LINE       164
 EXPRESSION (ep_in_hw ? rx_endp_i : '0)
             ----1---
-1-StatusTests
0CoveredT28,T20,T104
1CoveredT1,T2,T3

 LINE       175
 EXPRESSION (out_ep_enabled_i[out_ep_index_d] & ep_in_hw)
             ----------------1---------------   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT109,T107,T248
11CoveredT1,T2,T3

 LINE       178
 EXPRESSION (data_packet_received && ep_active && (rx_pid_i[3] != data_toggle_q[out_ep_index_d]))
             ----------1---------    ----2----    -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT107,T249,T172
110CoveredT1,T2,T3
111CoveredT29,T54,T61

 LINE       178
 SUB-EXPRESSION (rx_pid_i[3] != data_toggle_q[out_ep_index_d])
                -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       187
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT109,T110,T182
11CoveredT4,T18,T5

 LINE       189
 EXPRESSION (out_token_received && ep_active)
             ---------1--------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT109,T107,T200
11CoveredT1,T2,T27

 LINE       225
 EXPRESSION (ep_active && (out_token_received || (setup_token_received && ep_is_control)))
             ----1----    -------------------------------2-------------------------------
-1--2-StatusTests
01CoveredT109,T107,T200
10CoveredT1,T2,T3
11CoveredT1,T2,T27

 LINE       225
 SUB-EXPRESSION (out_token_received || (setup_token_received && ep_is_control))
                 ---------1--------    -------------------2-------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T18,T5
10CoveredT1,T2,T27

 LINE       225
 SUB-EXPRESSION (setup_token_received && ep_is_control)
                 ----------1---------    ------2------
-1--2-StatusTests
01CoveredT3,T31,T4
10CoveredT109,T250,T251
11CoveredT4,T18,T5

 LINE       241
 EXPRESSION (timeout_cntdown_q == '0)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T27
1Not Covered

 LINE       249
 EXPRESSION (((!ep_is_control)) && out_ep_iso_i[out_ep_index] && data_packet_received)
             ---------1--------    -------------2------------    ----------3---------
-1--2--3-StatusTests
011CoveredT61,T252,T253
101CoveredT1,T2,T27
110CoveredT61,T173,T254
111CoveredT61,T173,T254

 LINE       254
 EXPRESSION (bad_data_toggle && ((!out_ep_stall_i[out_ep_index])))
             -------1-------    ----------------2----------------
-1--2-StatusTests
01CoveredT1,T27,T28
10Not Covered
11CoveredT29,T54,T103

 LINE       261
 EXPRESSION (invalid_packet_received || non_data_packet_received)
             -----------1-----------    ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T27
01CoveredT82,T101
10CoveredT164,T215,T255

 LINE       278
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------
-1--2-StatusTests
00CoveredT4,T18,T5
01Not Covered
10Not Covered

 LINE       292
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------
-1--2-StatusTests
00CoveredT1,T27,T28
01Not Covered
10Not Covered

 LINE       307
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------
-1--2-StatusTests
00CoveredT61,T173,T254
01Not Covered
10Not Covered

 LINE       340
 EXPRESSION (link_reset_i ? StIdle : out_xact_state_next)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       348
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT109,T110,T182
11CoveredT4,T18,T5

 LINE       393
 EXPRESSION ((out_xact_state == StRcvdDataStart) && rx_data_put_i)
             -----------------1-----------------    ------2------
-1--2-StatusTests
01CoveredT3,T31,T19
10CoveredT1,T2,T27
11CoveredT1,T2,T27

 LINE       393
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T27

 LINE       405
 EXPRESSION ((out_xact_state == StIdle) || (out_xact_state == StRcvdOut))
             -------------1------------    --------------2--------------
-1--2-StatusTests
00CoveredT1,T2,T27
01CoveredT1,T2,T27
10CoveredT1,T2,T3

 LINE       405
 SUB-EXPRESSION (out_xact_state == StIdle)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T27
1CoveredT1,T2,T3

 LINE       405
 SUB-EXPRESSION (out_xact_state == StRcvdOut)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T27

 LINE       407
 EXPRESSION (out_ep_data_put_o && out_ep_full_i[out_ep_index])
             --------1--------    -------------2-------------
-1--2-StatusTests
01CoveredT40,T256,T109
10CoveredT1,T2,T27
11CoveredT256,T109,T150

 LINE       418
 EXPRESSION (((!nak_out_transaction)) && ((~&out_ep_put_addr_o)) && out_ep_data_put_o)
             ------------1-----------    -----------2-----------    --------3--------
-1--2--3-StatusTests
011CoveredT256,T109,T150
101CoveredT1,T27,T30
110CoveredT1,T2,T3
111CoveredT1,T2,T27

 LINE       424
 EXPRESSION (out_xact_state == StRcvdOut)
            --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T27

 LINE       426
 EXPRESSION ((out_xact_state == StRcvdDataStart) && increment_addr)
             -----------------1-----------------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T27
11CoveredT1,T2,T27

 LINE       426
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T27

 LINE       435
 EXPRESSION ((out_xact_state == StRcvdDataStart) && (ep_is_control || ((!out_ep_iso_i[out_ep_index]))) && ((!out_ep_stall_i[out_ep_index])) && bad_data_toggle)
             -----------------1-----------------    -------------------------2------------------------    ----------------3----------------    -------4-------
-1--2--3--4-StatusTests
0111CoveredT109,T110,T213
1011CoveredT61,T173,T252
1101Not Covered
1110CoveredT1,T27,T28
1111CoveredT29,T54,T103

 LINE       435
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T27

 LINE       435
 SUB-EXPRESSION (ep_is_control || ((!out_ep_iso_i[out_ep_index])))
                 ------1------    ---------------2---------------
-1--2-StatusTests
00CoveredT257,T61,T173
01CoveredT1,T2,T3
10CoveredT257,T61,T258

FSM Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe
Summary for FSM :: out_xact_state
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 8 8 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: out_xact_state
states   Line No.   Covered   Tests   
StIdle 340 Covered T1,T2,T3
StRcvdDataEnd 266 Covered T1,T2,T27
StRcvdDataStart 240 Covered T1,T2,T27
StRcvdIsoDataEnd 253 Covered T61,T173,T254
StRcvdOut 226 Covered T1,T2,T27


transitions   Line No.   Covered   Tests   
StIdle->StRcvdOut 226 Covered T1,T2,T27
StRcvdDataEnd->StIdle 340 Covered T1,T2,T27
StRcvdDataStart->StIdle 340 Covered T29,T54,T40
StRcvdDataStart->StRcvdDataEnd 266 Covered T1,T2,T27
StRcvdDataStart->StRcvdIsoDataEnd 253 Covered T61,T173,T254
StRcvdIsoDataEnd->StIdle 340 Covered T61,T173,T254
StRcvdOut->StIdle 340 Covered T259
StRcvdOut->StRcvdDataStart 240 Covered T1,T2,T27



Branch Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe
Line No.TotalCoveredPercent
Branches 52 49 94.23
TERNARY 164 2 2 100.00
IF 184 4 4 100.00
IF 196 3 3 100.00
CASE 221 17 14 82.35
IF 329 2 2 100.00
IF 337 3 3 100.00
IF 348 3 3 100.00
IF 354 2 2 100.00
IF 363 3 3 100.00
IF 373 3 3 100.00
IF 390 2 2 100.00
IF 402 4 4 100.00
IF 421 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 164 (ep_in_hw) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T28,T20,T104


LineNo. Expression -1-: 184 if ((!rst_ni)) -2-: 187 if ((setup_token_received && ep_active)) -3-: 189 if ((out_token_received && ep_active))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T4,T18,T5
0 0 1 Covered T1,T2,T27
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 196 if ((!rst_ni)) -2-: 199 if (rx_data_put_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 221 case (out_xact_state) -2-: 225 if ((ep_active && (out_token_received || (setup_token_received && ep_is_control)))) -3-: 239 if (rx_pkt_start_i) -4-: 241 if ((timeout_cntdown_q == '0)) -5-: 249 if ((((!ep_is_control) && out_ep_iso_i[out_ep_index]) && data_packet_received)) -6-: 254 if ((bad_data_toggle && (!out_ep_stall_i[out_ep_index]))) -7-: 261 if ((invalid_packet_received || non_data_packet_received)) -8-: 265 if (data_packet_received) -9-: 276 if (current_xact_setup_q) -10-: 278 if ((nak_out_transaction | out_ep_full_i[out_ep_index])) -11-: 289 if (out_ep_stall_i[out_ep_index]) -12-: 292 if ((nak_out_transaction | out_ep_full_i[out_ep_index])) -13-: 307 if ((nak_out_transaction | out_ep_full_i[out_ep_index]))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13-StatusTestsExclude Annotation
StIdle 1 - - - - - - - - - - - Covered T1,T2,T27
StIdle 0 - - - - - - - - - - - Covered T1,T2,T3
StRcvdOut - 1 - - - - - - - - - - Covered T1,T2,T27
StRcvdOut - 0 1 - - - - - - - - - Not Covered
StRcvdOut - 0 0 - - - - - - - - - Covered T1,T2,T27
StRcvdDataStart - - - 1 - - - - - - - - Covered T61,T173,T254
StRcvdDataStart - - - 0 1 - - - - - - - Covered T29,T54,T103
StRcvdDataStart - - - 0 0 1 - - - - - - Covered T164,T215,T255
StRcvdDataStart - - - 0 0 0 1 - - - - - Covered T1,T2,T27
StRcvdDataStart - - - 0 0 0 0 - - - - - Covered T1,T2,T27
StRcvdDataEnd - - - - - - - 1 1 - - - Not Covered
StRcvdDataEnd - - - - - - - 1 0 - - - Covered T4,T18,T5
StRcvdDataEnd - - - - - - - 0 - 1 - - Covered T2,T17,T23
StRcvdDataEnd - - - - - - - 0 - 0 1 - Covered T256,T109,T150
StRcvdDataEnd - - - - - - - 0 - 0 0 - Covered T1,T27,T28
StRcvdIsoDataEnd - - - - - - - - - - - 1 Not Covered
StRcvdIsoDataEnd - - - - - - - - - - - 0 Covered T61,T173,T254
default - - - - - - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 329 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 337 if ((!rst_ni)) -2-: 340 (link_reset_i) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 348 if ((setup_token_received && ep_active)) -2-: 350 if (new_pkt_end)

Branches:
-1--2-StatusTests
1 - Covered T4,T18,T5
0 1 Covered T1,T27,T28
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 354 if (out_datatog_we_i)

Branches:
-1-StatusTests
1 Covered T29,T54,T103
0 Covered T1,T2,T3


LineNo. Expression -1-: 363 if ((!rst_ni)) -2-: 365 if (link_reset_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 373 if ((!rst_ni)) -2-: 378 if (out_xact_start)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T27
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 390 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 402 if ((!rst_ni)) -2-: 405 if (((out_xact_state == StIdle) || (out_xact_state == StRcvdOut))) -3-: 407 if ((out_ep_data_put_o && out_ep_full_i[out_ep_index]))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T256,T109,T150
0 0 0 Covered T1,T2,T27


LineNo. Expression -1-: 421 if ((!rst_ni)) -2-: 424 if ((out_xact_state == StRcvdOut)) -3-: 426 if (((out_xact_state == StRcvdDataStart) && increment_addr))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T27
0 0 1 Covered T1,T2,T27
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutXactStateValid_A 579551765 579266161 0 0


OutXactStateValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 579551765 579266161 0 0
T1 55430 55371 0 0
T2 10663 10595 0 0
T3 33356 33302 0 0
T4 124760 124660 0 0
T27 548958 548906 0 0
T28 144634 144626 0 0
T29 17819 17768 0 0
T30 27050 26970 0 0
T31 15434 15369 0 0
T32 12075 12003 0 0