Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9333101	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9954554

1

T1

13

T2

14

T3

6061

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	18632466	1			T1	55		T2	66		T3	12019
values[0x0]	327394	1			T1	7		T2	10		T3	90
values[0x1]	327795	1			T1	9		T2	3		T3	94

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7418239	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

11869416

1

T1

29

T2

38

T3

7287

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55742	1			T2	1		T3	50		T14	1
valid_sources[0x01]	72078	1			T2	1		T3	70		T4	149
valid_sources[0x02]	65318	1			T3	45		T4	172		T68	1
valid_sources[0x03]	86123	1			T1	2		T3	46		T4	160
valid_sources[0x04]	55907	1			T2	1		T3	31		T4	155
valid_sources[0x05]	75822	1			T1	4		T3	59		T4	170
valid_sources[0x06]	64223	1			T3	49		T4	184		T7	2
valid_sources[0x07]	55493	1			T3	50		T4	146		T7	1
valid_sources[0x08]	55299	1			T1	2		T3	52		T4	135
valid_sources[0x09]	141571	1			T3	56		T4	143		T6	1
valid_sources[0x0a]	57347	1			T2	2		T3	48		T4	151
valid_sources[0x0b]	55089	1			T1	2		T2	1		T3	44
valid_sources[0x0c]	54873	1			T3	57		T4	159		T16	2
valid_sources[0x0d]	98157	1			T3	56		T4	148		T23	2
valid_sources[0x0e]	94989	1			T1	1		T3	51		T4	162
valid_sources[0x0f]	81386	1			T3	45		T4	162		T7	1
valid_sources[0x10]	55940	1			T3	55		T4	146		T7	1
valid_sources[0x11]	55559	1			T3	35		T4	155		T7	1
valid_sources[0x12]	56438	1			T3	64		T4	166		T23	3
valid_sources[0x13]	56647	1			T3	25		T4	152		T6	6
valid_sources[0x14]	103159	1			T1	1		T3	58		T4	141
valid_sources[0x15]	107494	1			T3	61		T4	147		T23	1
valid_sources[0x16]	55179	1			T3	49		T4	176		T7	2
valid_sources[0x17]	56018	1			T3	48		T4	138		T91	12
valid_sources[0x18]	70003	1			T3	36		T4	169		T23	2
valid_sources[0x19]	55541	1			T3	66		T4	192		T23	2
valid_sources[0x1a]	54990	1			T3	41		T4	150		T7	1
valid_sources[0x1b]	157524	1			T3	50		T4	150		T23	2
valid_sources[0x1c]	56125	1			T3	49		T4	167		T91	2
valid_sources[0x1d]	117476	1			T3	32		T4	135		T23	2
valid_sources[0x1e]	118354	1			T1	3		T3	42		T4	153
valid_sources[0x1f]	58047	1			T3	29		T14	4		T4	179
valid_sources[0x20]	128688	1			T3	48		T14	1		T4	162
valid_sources[0x21]	79585	1			T3	38		T14	1		T4	156
valid_sources[0x22]	55536	1			T3	40		T4	149		T91	7
valid_sources[0x23]	55731	1			T3	37		T4	130		T91	22
valid_sources[0x24]	74599	1			T3	43		T4	140		T23	1
valid_sources[0x25]	80029	1			T3	51		T4	149		T23	1
valid_sources[0x26]	56600	1			T3	50		T4	167		T25	5
valid_sources[0x27]	69546	1			T3	64		T4	143		T17	1
valid_sources[0x28]	55121	1			T3	56		T4	167		T23	1
valid_sources[0x29]	54923	1			T3	59		T4	153		T6	1
valid_sources[0x2a]	79749	1			T2	1		T3	46		T4	130
valid_sources[0x2b]	68027	1			T3	59		T4	161		T7	1
valid_sources[0x2c]	77570	1			T3	35		T4	135		T7	2
valid_sources[0x2d]	62580	1			T1	1		T3	45		T4	143
valid_sources[0x2e]	160298	1			T3	43		T4	138		T22	16
valid_sources[0x2f]	93899	1			T2	2		T3	55		T4	151
valid_sources[0x30]	55182	1			T2	2		T3	61		T4	141
valid_sources[0x31]	134921	1			T1	2		T3	30		T4	159
valid_sources[0x32]	71518	1			T2	1		T3	53		T4	136
valid_sources[0x33]	55735	1			T3	58		T4	171		T23	1
valid_sources[0x34]	54431	1			T3	42		T4	137		T6	5
valid_sources[0x35]	57020	1			T2	1		T3	38		T4	142
valid_sources[0x36]	55546	1			T3	39		T4	149		T7	1
valid_sources[0x37]	56274	1			T2	1		T3	65		T4	160
valid_sources[0x38]	55186	1			T3	36		T4	140		T68	1
valid_sources[0x39]	56555	1			T2	1		T3	52		T14	1
valid_sources[0x3a]	132244	1			T3	43		T14	1		T4	157
valid_sources[0x3b]	83138	1			T1	1		T3	58		T4	147
valid_sources[0x3c]	55578	1			T3	40		T4	183		T7	2
valid_sources[0x3d]	94019	1			T3	44		T4	122		T7	1
valid_sources[0x3e]	59477	1			T2	1		T3	47		T4	152
valid_sources[0x3f]	58392	1			T3	44		T4	179		T7	1
valid_sources[0x40]	58221	1			T3	56		T4	157		T91	14
valid_sources[0x41]	56345	1			T3	44		T4	148		T7	2
valid_sources[0x42]	76692	1			T3	36		T4	153		T7	2
valid_sources[0x43]	55806	1			T2	3		T3	54		T4	143
valid_sources[0x44]	54955	1			T3	52		T4	171		T23	2
valid_sources[0x45]	82591	1			T1	1		T3	48		T4	163
valid_sources[0x46]	55760	1			T2	1		T3	61		T4	156
valid_sources[0x47]	56543	1			T3	50		T4	134		T17	1
valid_sources[0x48]	291351	1			T3	41		T4	144		T6	2
valid_sources[0x49]	56239	1			T3	30		T4	148		T91	4
valid_sources[0x4a]	56352	1			T3	58		T4	132		T23	1
valid_sources[0x4b]	54871	1			T3	36		T4	151		T6	1
valid_sources[0x4c]	72100	1			T3	39		T4	141		T7	1
valid_sources[0x4d]	56436	1			T1	1		T3	46		T4	161
valid_sources[0x4e]	76861	1			T3	52		T4	162		T23	1
valid_sources[0x4f]	85159	1			T1	1		T2	1		T3	61
valid_sources[0x50]	54657	1			T1	2		T3	53		T4	143
valid_sources[0x51]	56834	1			T3	41		T4	155		T23	2
valid_sources[0x52]	57264	1			T3	39		T4	153		T7	2
valid_sources[0x53]	156032	1			T3	39		T4	152		T16	1
valid_sources[0x54]	55481	1			T2	3		T3	35		T4	164
valid_sources[0x55]	139250	1			T3	48		T4	149		T23	1
valid_sources[0x56]	143035	1			T2	2		T3	41		T4	166
valid_sources[0x57]	56058	1			T3	49		T4	131		T17	1
valid_sources[0x58]	55522	1			T1	1		T2	1		T3	49
valid_sources[0x59]	217930	1			T2	2		T3	49		T4	177
valid_sources[0x5a]	57779	1			T1	1		T3	71		T4	131
valid_sources[0x5b]	55748	1			T3	58		T4	123		T23	1
valid_sources[0x5c]	55222	1			T2	1		T3	45		T4	157
valid_sources[0x5d]	56003	1			T2	2		T3	37		T4	158
valid_sources[0x5e]	56452	1			T3	40		T4	153		T91	19
valid_sources[0x5f]	136305	1			T2	1		T3	45		T4	170
valid_sources[0x60]	57125	1			T3	58		T4	159		T7	1
valid_sources[0x61]	56389	1			T3	32		T4	163		T7	1
valid_sources[0x62]	56691	1			T1	9		T3	48		T4	140
valid_sources[0x63]	56027	1			T3	36		T4	170		T91	2
valid_sources[0x64]	72459	1			T1	1		T2	2		T3	39
valid_sources[0x65]	162206	1			T2	2		T3	42		T4	153
valid_sources[0x66]	55125	1			T3	41		T4	177		T91	1
valid_sources[0x67]	54984	1			T3	42		T4	120		T6	1
valid_sources[0x68]	56053	1			T3	45		T4	154		T90	1
valid_sources[0x69]	57185	1			T3	30		T4	129		T91	2
valid_sources[0x6a]	56433	1			T3	38		T4	189		T23	4
valid_sources[0x6b]	55221	1			T2	1		T3	47		T4	126
valid_sources[0x6c]	62712	1			T3	49		T4	156		T68	1
valid_sources[0x6d]	55955	1			T3	34		T4	155		T16	1
valid_sources[0x6e]	54342	1			T3	51		T4	166		T7	3
valid_sources[0x6f]	55985	1			T3	47		T4	150		T91	1
valid_sources[0x70]	58527	1			T3	52		T4	169		T17	1
valid_sources[0x71]	56179	1			T3	41		T4	144		T7	2
valid_sources[0x72]	147353	1			T2	1		T3	45		T4	154
valid_sources[0x73]	56186	1			T3	49		T4	157		T23	2
valid_sources[0x74]	155111	1			T3	31		T14	1		T4	169
valid_sources[0x75]	56533	1			T3	48		T4	147		T91	1
valid_sources[0x76]	77535	1			T1	3		T3	46		T4	176
valid_sources[0x77]	69433	1			T2	1		T3	51		T4	150
valid_sources[0x78]	62297	1			T2	1		T3	47		T4	138
valid_sources[0x79]	71725	1			T2	1		T3	81		T4	163
valid_sources[0x7a]	56236	1			T3	48		T4	165		T91	1
valid_sources[0x7b]	56020	1			T3	61		T4	167		T23	2
valid_sources[0x7c]	55471	1			T3	54		T4	141		T23	2
valid_sources[0x7d]	56092	1			T3	45		T4	141		T6	4
valid_sources[0x7e]	55961	1			T3	32		T4	157		T26	1
valid_sources[0x7f]	56247	1			T3	41		T4	165		T25	16
valid_sources[0x80]	56641	1			T3	61		T4	156		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9421705

1

T1

3

T2

2

T3

5939

values[0x0]

all_enables

biggest_size

275370

1

T1

5

T2

9

T3

63

values[0x1]

all_enables

biggest_size

257479

1

T1

5

T2

3

T3

59