Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

9347234

1

T1

58

T2

65

T3

6142

full_word

9955416

1

T1

13

T2

14

T3

6061

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	19302360	1			T1	71		T2	79		T3	12203
auto[TlIntgErrCmd]	101	1			T230	7		T254	1		T361	2
auto[TlIntgErrData]	92	1			T229	3		T230	6		T254	3
auto[TlIntgErrBoth]	97	1			T229	7		T230	7		T254	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18634225

1

T1

55

T2

66

T3

12019

auto[1]

668425

1

T1

16

T2

13

T3

184

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9212245	1			T1	52		T2	64		T3	6080
auto[TlIntgErrNone]	partial	auto[1]	134713	1			T1	6		T2	1		T3	62
auto[TlIntgErrNone]	full_word	auto[0]	9421868	1			T1	3		T2	2		T3	5939
auto[TlIntgErrNone]	full_word	auto[1]	533534	1			T1	10		T2	12		T3	122
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T230	6		T254	1		T361	2
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T230	1		T317	1		T319	6
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T362	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	35	1			T229	1		T230	5		T254	2
auto[TlIntgErrData]	partial	auto[1]	51	1			T229	1		T230	1		T254	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T229	1		T363	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T319	1		T364	1		T365	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T229	6		T230	4		T254	2
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T229	1		T230	2		T254	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T254	1		T365	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T230	1		T319	1		T365	1