Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9109133	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9743242

1

T1

14

T2

9770

T3

69

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	18197269	1			T1	76		T2	5353		T3	45
values[0x0]	326327	1			T1	10		T2	2439		T3	25
values[0x1]	328779	1			T1	9		T2	2466		T3	32

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7239944	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

11612431

1

T1

40

T2

9850

T3

81

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	58223	1			T2	28		T19	1		T20	3
valid_sources[0x01]	161453	1			T2	16		T22	25		T27	1
valid_sources[0x02]	66625	1			T2	48		T20	2		T22	22
valid_sources[0x03]	184575	1			T2	46		T19	1		T22	17
valid_sources[0x04]	56704	1			T2	44		T17	3		T19	1
valid_sources[0x05]	55907	1			T2	59		T17	1		T20	1
valid_sources[0x06]	113168	1			T2	58		T19	3		T22	20
valid_sources[0x07]	193960	1			T2	51		T22	22		T4	153
valid_sources[0x08]	157677	1			T2	82		T18	3		T22	29
valid_sources[0x09]	134887	1			T2	31		T22	23		T4	174
valid_sources[0x0a]	55312	1			T2	38		T17	1		T20	1
valid_sources[0x0b]	63622	1			T2	25		T17	1		T18	1
valid_sources[0x0c]	57764	1			T2	53		T17	1		T22	26
valid_sources[0x0d]	56594	1			T2	47		T20	2		T22	20
valid_sources[0x0e]	55906	1			T2	45		T20	1		T22	21
valid_sources[0x0f]	55683	1			T2	50		T17	1		T22	27
valid_sources[0x10]	66597	1			T2	45		T17	2		T22	12
valid_sources[0x11]	80233	1			T2	46		T20	2		T22	21
valid_sources[0x12]	70394	1			T2	39		T22	17		T4	185
valid_sources[0x13]	81094	1			T2	44		T22	41		T27	1
valid_sources[0x14]	56236	1			T2	76		T19	1		T22	26
valid_sources[0x15]	55932	1			T2	24		T22	39		T4	152
valid_sources[0x16]	55977	1			T2	22		T17	1		T20	1
valid_sources[0x17]	59981	1			T2	24		T20	3		T22	25
valid_sources[0x18]	72136	1			T2	71		T17	1		T20	1
valid_sources[0x19]	65480	1			T2	22		T19	1		T22	27
valid_sources[0x1a]	72952	1			T2	36		T22	19		T4	196
valid_sources[0x1b]	56443	1			T2	33		T17	2		T19	1
valid_sources[0x1c]	117914	1			T2	46		T19	3		T22	24
valid_sources[0x1d]	59461	1			T2	40		T17	3		T22	29
valid_sources[0x1e]	101807	1			T2	58		T17	4		T22	23
valid_sources[0x1f]	56225	1			T2	51		T17	1		T22	32
valid_sources[0x20]	72196	1			T2	46		T20	3		T22	24
valid_sources[0x21]	121677	1			T2	27		T17	1		T21	89
valid_sources[0x22]	64398	1			T2	36		T22	25		T4	179
valid_sources[0x23]	55977	1			T2	21		T20	2		T22	22
valid_sources[0x24]	56148	1			T2	29		T17	1		T22	23
valid_sources[0x25]	125676	1			T2	31		T17	2		T22	32
valid_sources[0x26]	56672	1			T2	35		T22	28		T4	216
valid_sources[0x27]	89080	1			T2	52		T17	1		T22	24
valid_sources[0x28]	55405	1			T2	34		T20	2		T22	27
valid_sources[0x29]	184977	1			T2	47		T17	3		T18	1
valid_sources[0x2a]	55832	1			T2	38		T17	1		T18	1
valid_sources[0x2b]	73698	1			T2	41		T22	24		T4	150
valid_sources[0x2c]	56270	1			T2	57		T19	3		T20	1
valid_sources[0x2d]	58262	1			T2	55		T18	1		T22	21
valid_sources[0x2e]	58310	1			T2	41		T22	32		T4	199
valid_sources[0x2f]	69314	1			T2	33		T20	1		T22	27
valid_sources[0x30]	55478	1			T2	57		T17	1		T19	1
valid_sources[0x31]	67498	1			T2	32		T17	1		T19	1
valid_sources[0x32]	56089	1			T2	38		T19	2		T20	2
valid_sources[0x33]	181145	1			T2	45		T20	1		T22	13
valid_sources[0x34]	55767	1			T2	28		T22	36		T4	193
valid_sources[0x35]	56510	1			T2	16		T19	2		T20	2
valid_sources[0x36]	55151	1			T2	33		T17	9		T22	23
valid_sources[0x37]	56524	1			T2	39		T17	1		T20	2
valid_sources[0x38]	57308	1			T2	49		T20	1		T22	19
valid_sources[0x39]	55798	1			T2	50		T22	27		T4	183
valid_sources[0x3a]	158533	1			T2	38		T17	2		T19	1
valid_sources[0x3b]	168740	1			T2	44		T17	2		T20	5
valid_sources[0x3c]	56983	1			T2	43		T22	15		T4	171
valid_sources[0x3d]	56052	1			T2	28		T20	1		T22	9
valid_sources[0x3e]	56695	1			T2	48		T20	2		T22	16
valid_sources[0x3f]	67835	1			T2	52		T19	1		T22	34
valid_sources[0x40]	101936	1			T2	48		T20	1		T22	19
valid_sources[0x41]	98066	1			T2	33		T20	1		T22	27
valid_sources[0x42]	56193	1			T2	39		T20	1		T22	27
valid_sources[0x43]	56690	1			T2	20		T22	28		T4	220
valid_sources[0x44]	56906	1			T2	19		T20	2		T22	15
valid_sources[0x45]	56701	1			T2	38		T18	1		T22	16
valid_sources[0x46]	56409	1			T2	53		T22	27		T4	221
valid_sources[0x47]	68437	1			T2	23		T17	1		T22	30
valid_sources[0x48]	58003	1			T2	47		T20	1		T22	26
valid_sources[0x49]	55391	1			T2	39		T22	16		T4	165
valid_sources[0x4a]	182488	1			T2	65		T20	1		T22	15
valid_sources[0x4b]	132115	1			T2	31		T19	1		T22	15
valid_sources[0x4c]	56139	1			T2	38		T17	1		T19	1
valid_sources[0x4d]	78333	1			T2	57		T17	1		T19	1
valid_sources[0x4e]	89780	1			T2	24		T22	24		T4	174
valid_sources[0x4f]	74011	1			T2	44		T22	23		T4	168
valid_sources[0x50]	56407	1			T2	46		T22	29		T4	212
valid_sources[0x51]	142595	1			T2	34		T20	2		T22	31
valid_sources[0x52]	56140	1			T2	38		T18	2		T19	2
valid_sources[0x53]	55930	1			T2	22		T17	4		T22	37
valid_sources[0x54]	55726	1			T2	47		T19	1		T22	26
valid_sources[0x55]	56511	1			T2	55		T17	1		T20	2
valid_sources[0x56]	56687	1			T2	45		T20	1		T22	32
valid_sources[0x57]	56887	1			T2	50		T17	1		T20	3
valid_sources[0x58]	57531	1			T2	34		T17	1		T22	16
valid_sources[0x59]	57422	1			T2	52		T17	2		T19	2
valid_sources[0x5a]	120338	1			T2	48		T17	1		T19	1
valid_sources[0x5b]	56770	1			T2	24		T22	27		T4	174
valid_sources[0x5c]	56732	1			T2	41		T22	19		T4	185
valid_sources[0x5d]	57094	1			T2	47		T19	2		T22	23
valid_sources[0x5e]	55369	1			T2	25		T22	20		T4	180
valid_sources[0x5f]	126890	1			T2	44		T19	1		T22	31
valid_sources[0x60]	165887	1			T2	47		T22	33		T4	230
valid_sources[0x61]	58060	1			T2	45		T18	1		T19	2
valid_sources[0x62]	61118	1			T2	22		T19	3		T22	29
valid_sources[0x63]	62457	1			T2	17		T22	25		T61	104
valid_sources[0x64]	54621	1			T2	55		T17	4		T22	22
valid_sources[0x65]	55315	1			T2	31		T20	2		T22	32
valid_sources[0x66]	56865	1			T2	23		T19	3		T20	1
valid_sources[0x67]	56528	1			T2	41		T20	2		T22	29
valid_sources[0x68]	56648	1			T1	95		T2	39		T22	20
valid_sources[0x69]	56391	1			T2	43		T19	2		T22	35
valid_sources[0x6a]	55140	1			T2	35		T17	1		T19	2
valid_sources[0x6b]	55570	1			T2	73		T17	2		T22	20
valid_sources[0x6c]	56859	1			T2	43		T20	1		T22	25
valid_sources[0x6d]	65164	1			T2	66		T20	3		T22	23
valid_sources[0x6e]	161454	1			T2	53		T17	1		T19	1
valid_sources[0x6f]	59769	1			T2	34		T22	24		T4	200
valid_sources[0x70]	142689	1			T2	49		T22	26		T4	185
valid_sources[0x71]	55531	1			T2	47		T20	1		T22	26
valid_sources[0x72]	56796	1			T2	46		T22	40		T4	161
valid_sources[0x73]	67308	1			T2	26		T19	1		T20	1
valid_sources[0x74]	62866	1			T2	30		T20	1		T22	34
valid_sources[0x75]	54829	1			T2	34		T18	1		T22	35
valid_sources[0x76]	80996	1			T2	33		T20	1		T22	26
valid_sources[0x77]	56275	1			T2	50		T17	1		T22	28
valid_sources[0x78]	75235	1			T2	24		T22	24		T4	202
valid_sources[0x79]	62496	1			T2	37		T19	1		T22	24
valid_sources[0x7a]	56015	1			T2	13		T19	1		T20	4
valid_sources[0x7b]	62823	1			T2	25		T20	1		T22	23
valid_sources[0x7c]	55958	1			T2	43		T19	1		T22	27
valid_sources[0x7d]	78724	1			T2	61		T20	3		T22	14
valid_sources[0x7e]	58575	1			T2	45		T17	2		T18	1
valid_sources[0x7f]	56804	1			T2	43		T17	1		T20	1
valid_sources[0x80]	55890	1			T2	37		T22	27		T4	228

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9208102

1

T1

2

T2

5156

T3

31

values[0x0]

all_enables

biggest_size

275378

1

T1

7

T2

2285

T3

20

values[0x1]

all_enables

biggest_size

259762

1

T1

5

T2

2329

T3

18