Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

9121879

1

T1

81

T2

488

T3

33

full_word

9744127

1

T1

14

T2

9770

T3

69

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	18865706	1			T1	95		T2	10258		T3	102
auto[TlIntgErrCmd]	104	1			T269	2		T270	6		T278	8
auto[TlIntgErrData]	109	1			T269	4		T270	9		T278	5
auto[TlIntgErrBoth]	87	1			T269	4		T270	5		T278	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18198964

1

T1

76

T2

5353

T3

45

auto[1]

667042

1

T1

19

T2

4905

T3

57

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8990540	1			T1	74		T2	197		T3	14
auto[TlIntgErrNone]	partial	auto[1]	131067	1			T1	7		T2	291		T3	19
auto[TlIntgErrNone]	full_word	auto[0]	9208289	1			T1	2		T2	5156		T3	31
auto[TlIntgErrNone]	full_word	auto[1]	535810	1			T1	12		T2	4614		T3	38
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T269	1		T270	3		T278	3
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T270	3		T278	3		T510	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T278	2		T514	1		T509	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T269	1		T514	1		T515	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T269	4		T270	4		T278	2
auto[TlIntgErrData]	partial	auto[1]	49	1			T270	4		T278	3		T510	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T516	1		T515	1		T508	2
auto[TlIntgErrData]	full_word	auto[1]	7	1			T270	1		T514	1		T511	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1			T269	2		T270	1		T278	3
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T269	2		T270	2		T278	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T270	1		T278	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T270	1		T517	1		-	-