Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	584202707	10324	0	0
ep_in_enable_rd_A	584202707	2665	0	0
ep_out_enable_rd_A	584202707	3111	0	0
in_iso_rd_A	584202707	2928	0	0
intr_enable_rd_A	584202707	4036	0	0
out_iso_rd_A	584202707	2638	0	0
phy_config_rd_A	584202707	1642	0	0
phy_pins_drive_rd_A	584202707	2210	0	0
rxenable_setup_rd_A	584202707	2690	0	0
set_nak_out_rd_A	584202707	3000	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	10324	0	0
T241	5008	15	0	0
T242	6901	329	0	0
T243	3982	7	0	0
T268	4390	572	0	0
T269	14962	3	0	0
T270	60052	2	0	0
T279	4411	22	0	0
T280	5693	821	0	0
T283	6394	255	0	0
T288	6653	14	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	2665	0	0
T290	4870	8	0	0
T322	9107	21	0	0
T327	15844	48	0	0
T328	4187	55	0	0
T329	7176	20	0	0
T330	12896	29	0	0
T331	11817	26	0	0
T332	10788	42	0	0
T333	18747	272	0	0
T334	5103	50	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	3111	0	0
T290	4870	55	0	0
T322	9107	15	0	0
T327	15844	53	0	0
T328	4187	1	0	0
T330	12896	3	0	0
T331	11817	7	0	0
T332	10788	56	0	0
T333	18747	196	0	0
T334	5103	44	0	0
T335	3306	3	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	2928	0	0
T290	4870	49	0	0
T320	3083	35	0	0
T322	9107	1	0	0
T327	15844	52	0	0
T328	4187	13	0	0
T330	12896	27	0	0
T331	11817	22	0	0
T332	10788	32	0	0
T333	18747	245	0	0
T334	5103	45	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	4036	0	0
T249	2767	3	0	0
T290	4870	13	0	0
T320	3083	8	0	0
T322	9107	17	0	0
T327	15844	35	0	0
T328	4187	84	0	0
T329	7176	12	0	0
T330	12896	26	0	0
T336	1704	14	0	0
T337	2063	10	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	2638	0	0
T290	4870	37	0	0
T320	3083	44	0	0
T322	9107	25	0	0
T327	15844	46	0	0
T328	4187	38	0	0
T329	7176	31	0	0
T330	12896	29	0	0
T331	11817	12	0	0
T332	10788	28	0	0
T333	18747	108	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	1642	0	0
T290	4870	5	0	0
T320	3083	3	0	0
T322	9107	7	0	0
T327	15844	69	0	0
T328	4187	49	0	0
T330	12896	32	0	0
T331	11817	20	0	0
T332	10788	37	0	0
T333	18747	88	0	0
T334	5103	8	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	2210	0	0
T290	4870	12	0	0
T320	3083	4	0	0
T322	9107	24	0	0
T327	15844	50	0	0
T328	4187	31	0	0
T329	7176	6	0	0
T330	12896	27	0	0
T331	11817	3	0	0
T332	10788	54	0	0
T333	18747	220	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	2690	0	0
T290	4870	5	0	0
T322	9107	33	0	0
T327	15844	36	0	0
T328	4187	13	0	0
T329	7176	12	0	0
T330	12896	28	0	0
T331	11817	15	0	0
T332	10788	44	0	0
T333	18747	224	0	0
T334	5103	2	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	3000	0	0
T290	4870	32	0	0
T320	3083	41	0	0
T322	9107	24	0	0
T327	15844	100	0	0
T328	4187	45	0	0
T329	7176	18	0	0
T330	12896	9	0	0
T331	11817	18	0	0
T332	10788	22	0	0
T333	18747	127	0	0