Unified Coverage Report :: Module Instance :: tb.dut.usbdev_avsetupfifo

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	96.77			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	96.77			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	98.59	88.57			96.00	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	98.59	88.57			96.00	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	98.59	88.57			96.00	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T3,T17,T19

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T53,T54,T84
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T17,T19

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T3,T17,T19
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T17,T19

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T17,T19
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	582415869	128475410	0	0
DepthKnown_A	582415869	582130369	0	0
RvalidKnown_A	582415869	582130369	0	0
WreadyKnown_A	582415869	582130369	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	582415869	128475410	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	128475410	0	0
T3	26989	1682	0	0
T4	0	96369	0	0
T5	0	94437	0	0
T6	0	112987	0	0
T17	31389	1689	0	0
T18	13709	0	0	0
T19	19816	1673	0	0
T20	33285	0	0	0
T21	25570	1700	0	0
T22	20605	0	0	0
T23	7294	0	0	0
T27	21495	1675	0	0
T61	27509	1667	0	0
T83	0	24068	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	582130369	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	582130369	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	582130369	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	128475410	0	0
T3	26989	1682	0	0
T4	0	96369	0	0
T5	0	94437	0	0
T6	0	112987	0	0
T17	31389	1689	0	0
T18	13709	0	0	0
T19	19816	1673	0	0
T20	33285	0	0	0
T21	25570	1700	0	0
T22	20605	0	0	0
T23	7294	0	0	0
T27	21495	1675	0	0
T61	27509	1667	0	0
T83	0	24068	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T52,T85
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	582415869	278784461	0	0
DepthKnown_A	582415869	582130369	0	0
RvalidKnown_A	582415869	582130369	0	0
WreadyKnown_A	582415869	582130369	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	582415869	278784461	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	278784461	0	0
T1	147621	770	0	0
T2	913848	563890	0	0
T3	26989	3660	0	0
T17	31389	3252	0	0
T18	13709	2357	0	0
T19	19816	2904	0	0
T20	33285	24993	0	0
T21	25570	2106	0	0
T22	20605	0	0	0
T23	7294	1303	0	0
T27	0	2019	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	582130369	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	582130369	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	582130369	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	278784461	0	0
T1	147621	770	0	0
T2	913848	563890	0	0
T3	26989	3660	0	0
T17	31389	3252	0	0
T18	13709	2357	0	0
T19	19816	2904	0	0
T20	33285	24993	0	0
T21	25570	2106	0	0
T22	20605	0	0	0
T23	7294	1303	0	0
T27	0	2019	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	582415869	42919964	0	0
DepthKnown_A	582415869	582130369	0	0
RvalidKnown_A	582415869	582130369	0	0
WreadyKnown_A	582415869	582130369	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	582415869	42919964	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	42919964	0	0
T1	147621	112	0	0
T2	913848	37965	0	0
T3	26989	618	0	0
T17	31389	612	0	0
T18	13709	3440	0	0
T19	19816	591	0	0
T20	33285	1037	0	0
T21	25570	607	0	0
T22	20605	0	0	0
T23	7294	0	0	0
T27	0	591	0	0
T61	0	618	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	582130369	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	582130369	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	582130369	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	42919964	0	0
T1	147621	112	0	0
T2	913848	37965	0	0
T3	26989	618	0	0
T17	31389	612	0	0
T18	13709	3440	0	0
T19	19816	591	0	0
T20	33285	1037	0	0
T21	25570	607	0	0
T22	20605	0	0	0
T23	7294	0	0	0
T27	0	591	0	0
T61	0	618	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584202707	19183658	0	0
DepthKnown_A	584202707	583876648	0	0
RvalidKnown_A	584202707	583876648	0	0
WreadyKnown_A	584202707	583876648	0	0
gen_passthru_fifo.paramCheckPass	3738	3738	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	19183658	0	0
T1	147621	95	0	0
T2	913848	10413	0	0
T3	26989	102	0	0
T17	31389	139	0	0
T18	13709	16	0	0
T19	19816	96	0	0
T20	33285	189	0	0
T21	25570	89	0	0
T22	20605	6183	0	0
T23	7294	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	583876648	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	583876648	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	583876648	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3738	3738	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584202707	27508135	0	0
DepthKnown_A	584202707	583876648	0	0
RvalidKnown_A	584202707	583876648	0	0
WreadyKnown_A	584202707	583876648	0	0
gen_passthru_fifo.paramCheckPass	3738	3738	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	27508135	0	0
T1	147621	301	0	0
T2	913848	10258	0	0
T3	26989	417	0	0
T17	31389	139	0	0
T18	13709	16	0	0
T19	19816	96	0	0
T20	33285	189	0	0
T21	25570	89	0	0
T22	20605	6183	0	0
T23	7294	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	583876648	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	583876648	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	583876648	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3738	3738	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584202707	977704	0	0
DepthKnown_A	584202707	583876648	0	0
RvalidKnown_A	584202707	583876648	0	0
WreadyKnown_A	584202707	583876648	0	0
gen_passthru_fifo.paramCheckPass	3738	3738	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	977704	0	0
T2	913848	8592	0	0
T3	26989	44	0	0
T17	31389	78	0	0
T18	13709	0	0	0
T19	19816	38	0	0
T20	33285	144	0	0
T21	25570	33	0	0
T22	20605	0	0	0
T23	7294	0	0	0
T27	21495	56	0	0
T36	0	106	0	0
T61	0	48	0	0
T81	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	583876648	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	583876648	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	583876648	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3738	3738	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584202707	1661005	0	0
DepthKnown_A	584202707	583876648	0	0
RvalidKnown_A	584202707	583876648	0	0
WreadyKnown_A	584202707	583876648	0	0
gen_passthru_fifo.paramCheckPass	3738	3738	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	1661005	0	0
T2	913848	8592	0	0
T3	26989	173	0	0
T17	31389	78	0	0
T18	13709	0	0	0
T19	19816	38	0	0
T20	33285	144	0	0
T21	25570	33	0	0
T22	20605	0	0	0
T23	7294	0	0	0
T27	21495	56	0	0
T36	0	106	0	0
T61	0	48	0	0
T81	0	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	583876648	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	583876648	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	583876648	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3738	3738	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584202707	18148895	0	0
DepthKnown_A	584202707	583876648	0	0
RvalidKnown_A	584202707	583876648	0	0
WreadyKnown_A	584202707	583876648	0	0
gen_passthru_fifo.paramCheckPass	3738	3738	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	18148895	0	0
T1	147621	95	0	0
T2	913848	1666	0	0
T3	26989	58	0	0
T17	31389	61	0	0
T18	13709	16	0	0
T19	19816	58	0	0
T20	33285	45	0	0
T21	25570	56	0	0
T22	20605	6183	0	0
T23	7294	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	583876648	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	583876648	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	583876648	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3738	3738	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584202707	25847130	0	0
DepthKnown_A	584202707	583876648	0	0
RvalidKnown_A	584202707	583876648	0	0
WreadyKnown_A	584202707	583876648	0	0
gen_passthru_fifo.paramCheckPass	3738	3738	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	25847130	0	0
T1	147621	301	0	0
T2	913848	1666	0	0
T3	26989	244	0	0
T17	31389	61	0	0
T18	13709	16	0	0
T19	19816	58	0	0
T20	33285	45	0	0
T21	25570	56	0	0
T22	20605	6183	0	0
T23	7294	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	583876648	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	583876648	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	583876648	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3738	3738	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T3,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T2,T3,T17
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T3,T17

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T17

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	582415869	1616471	0	0
DepthKnown_A	582415869	582130369	0	0
RvalidKnown_A	582415869	582130369	0	0
WreadyKnown_A	582415869	582130369	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	582415869	1616471	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	1616471	0	0
T2	913848	8592	0	0
T3	26989	173	0	0
T17	31389	78	0	0
T18	13709	0	0	0
T19	19816	38	0	0
T20	33285	144	0	0
T21	25570	33	0	0
T22	20605	0	0	0
T23	7294	0	0	0
T27	21495	56	0	0
T36	0	106	0	0
T61	0	48	0	0
T81	0	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	582130369	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	582130369	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	582130369	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	1616471	0	0
T2	913848	8592	0	0
T3	26989	173	0	0
T17	31389	78	0	0
T18	13709	0	0	0
T19	19816	38	0	0
T20	33285	144	0	0
T21	25570	33	0	0
T22	20605	0	0	0
T23	7294	0	0	0
T27	21495	56	0	0
T36	0	106	0	0
T61	0	48	0	0
T81	0	71	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T3,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T3,T17

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T17

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	582415869	627372	0	0
DepthKnown_A	582415869	582130369	0	0
RvalidKnown_A	582415869	582130369	0	0
WreadyKnown_A	582415869	582130369	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	582415869	627372	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	627372	0	0
T2	913848	4947	0	0
T3	26989	28	0	0
T17	31389	25	0	0
T18	13709	0	0	0
T19	19816	23	0	0
T20	33285	144	0	0
T21	25570	16	0	0
T22	20605	0	0	0
T23	7294	0	0	0
T27	21495	15	0	0
T36	0	106	0	0
T61	0	32	0	0
T81	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	582130369	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	582130369	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	582130369	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	627372	0	0
T2	913848	4947	0	0
T3	26989	28	0	0
T17	31389	25	0	0
T18	13709	0	0	0
T19	19816	23	0	0
T20	33285	144	0	0
T21	25570	16	0	0
T22	20605	0	0	0
T23	7294	0	0	0
T27	21495	15	0	0
T36	0	106	0	0
T61	0	32	0	0
T81	0	16	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	18	18	100.00
Logical	18	18	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T81,T82
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T3,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T2,T3,T17
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T3,T17

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T17

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T81,T82
1	0	Covered	T2,T3,T17
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T17

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	582415869	1064872	0	0
DepthKnown_A	582415869	582130369	0	0
RvalidKnown_A	582415869	582130369	0	0
WreadyKnown_A	582415869	582130369	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	582415869	1064872	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	1064872	0	0
T2	913848	4947	0	0
T3	26989	125	0	0
T17	31389	25	0	0
T18	13709	0	0	0
T19	19816	23	0	0
T20	33285	144	0	0
T21	25570	16	0	0
T22	20605	0	0	0
T23	7294	0	0	0
T27	21495	15	0	0
T36	0	106	0	0
T61	0	32	0	0
T81	0	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	582130369	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	582130369	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	582130369	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	582415869	1064872	0	0
T2	913848	4947	0	0
T3	26989	125	0	0
T17	31389	25	0	0
T18	13709	0	0	0
T19	19816	23	0	0
T20	33285	144	0	0
T21	25570	16	0	0
T22	20605	0	0	0
T23	7294	0	0	0
T27	21495	15	0	0
T36	0	106	0	0
T61	0	32	0	0
T81	0	71	0	0