Unified Coverage Report :: Module :: usbdev_counter

Module : usbdev_counter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.28	81.58	36.67			59.60

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctr_out	54.65	78.95	25.00			60.00
tb.dut.u_ctr_in	54.65	78.95	25.00			60.00
tb.dut.u_ctr_errors	65.57	84.21	50.00			62.50
tb.dut.u_ctr_nodata_in	66.96	84.21	50.00			66.67

---

Module Instance : tb.dut.u_ctr_out

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
54.65	78.95	25.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
54.65	78.95	25.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctr_in

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
54.65	78.95	25.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
54.65	78.95	25.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctr_errors

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.57	84.21	50.00			62.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.57	84.21	50.00			62.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctr_nodata_in

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.96	84.21	50.00			66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.96	84.21	50.00			66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : usbdev_counter ( parameter NEndpoints=12,NEvents=4,Width=8,EpW=4 )
Line Coverage for Module self-instances :

SCORE	LINE
54.65	78.95

tb.dut.u_ctr_out

	Line No.	Total	Covered	Percent
TOTAL		19	15	78.95
ALWAYS	45	7	5	71.43
CONT_ASSIGN	58	1	1	100.00
ALWAYS	70	8	6	75.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
46	1	1
47	1	1
50	1	2
			MISSING_ELSE
51	1	2
			MISSING_ELSE
58	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	0	1
78	1	2
			MISSING_ELSE
80	1	1
84	1	1
85	1	1
86	1	1

---

Line Coverage for Module : usbdev_counter ( parameter NEndpoints=1,NEvents=4,Width=8,EpW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
65.57	84.21

tb.dut.u_ctr_errors

	Line No.	Total	Covered	Percent
TOTAL		19	16	84.21
ALWAYS	45	7	6	85.71
CONT_ASSIGN	61	0	0
CONT_ASSIGN	62	1	1	100.00
ALWAYS	70	8	6	75.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
46	1	1
47	1	1
50	2	2
			==> MISSING_ELSE
51	1	2
			MISSING_ELSE
61		unreachable
62	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	0	1
78	1	2
			MISSING_ELSE
80	1	1
84	1	1
85	1	1
86	1	1

---

Line Coverage for Module : usbdev_counter ( parameter NEndpoints=12,NEvents=3,Width=8,EpW=4 )
Line Coverage for Module self-instances :

SCORE	LINE
54.65	78.95

tb.dut.u_ctr_in

	Line No.	Total	Covered	Percent
TOTAL		19	15	78.95
ALWAYS	45	7	5	71.43
CONT_ASSIGN	58	1	1	100.00
ALWAYS	70	8	6	75.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
46	1	1
47	1	1
50	1	2
			MISSING_ELSE
51	1	2
			MISSING_ELSE
58	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	0	1
78	1	2
			MISSING_ELSE
80	1	1
84	1	1
85	1	1
86	1	1

---

Line Coverage for Module : usbdev_counter ( parameter NEndpoints=12,NEvents=1,Width=8,EpW=4 )
Line Coverage for Module self-instances :

SCORE	LINE
66.96	84.21

tb.dut.u_ctr_nodata_in

	Line No.	Total	Covered	Percent
TOTAL		19	16	84.21
ALWAYS	45	7	6	85.71
CONT_ASSIGN	58	1	1	100.00
ALWAYS	70	8	6	75.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
46	1	1
47	1	1
50	1	2
			MISSING_ELSE
51	2	2
			==> MISSING_ELSE
58	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	0	1
78	1	2
			MISSING_ELSE
80	1	1
84	1	1
85	1	1
86	1	1

---

Cond Coverage for Module : usbdev_counter ( parameter NEndpoints=12,NEvents=4,Width=8,EpW=4 + NEndpoints=12,NEvents=3,Width=8,EpW=4 + NEndpoints=12,NEvents=1,Width=8,EpW=4 )
Cond Coverage for Module self-instances :

SCORE	COND
54.65	25.00

tb.dut.u_ctr_out

SCORE	COND
54.65	25.00

tb.dut.u_ctr_in

SCORE	COND
66.96	50.00

tb.dut.u_ctr_nodata_in

	Total	Covered	Percent
Conditions	5	2	40.00
Logical	5	2	40.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION ((ep_i < 4'(NEndpoints)) ? endpoints[ep_i] : 1'b0)
             -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (((|((ev_enables & event_i) & (~event_q)))) & ep_enabled)
             ---------------------1--------------------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Not Covered

---

Cond Coverage for Module : usbdev_counter ( parameter NEndpoints=1,NEvents=4,Width=8,EpW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
65.57	50.00

tb.dut.u_ctr_errors

	Total	Covered	Percent
Conditions	3	1	33.33
Logical	3	1	33.33
Non-Logical	0	0
Event	0	0

 LINE       78
 EXPRESSION (((|((ev_enables & event_i) & (~event_q)))) & ep_enabled)
             ---------------------1--------------------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Module : usbdev_counter ( parameter NEndpoints=12,NEvents=4,Width=8,EpW=4 + NEndpoints=12,NEvents=3,Width=8,EpW=4 + NEndpoints=12,NEvents=1,Width=8,EpW=4 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
54.65	60.00

tb.dut.u_ctr_out

SCORE	BRANCH
54.65	60.00

tb.dut.u_ctr_in

SCORE	BRANCH
66.96	66.67

tb.dut.u_ctr_nodata_in

	Line No.	Total	Covered	Percent
Branches		11	7	63.64
TERNARY	58	2	1	50.00
IF	45	5	4	80.00
IF	70	4	2	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	58	((ep_i < 4'(NEndpoints))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	45	if ((!rst_ni))
-2-:	50	if (endp_qe_i)
-3-:	51	if (ev_qe_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	73	if (reset_i)
-3-:	78	if (((|((ev_enables & event_i) & (~event_q))) & ep_enabled))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

---

Branch Coverage for Module : usbdev_counter ( parameter NEndpoints=1,NEvents=4,Width=8,EpW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
65.57	62.50

tb.dut.u_ctr_errors

	Line No.	Total	Covered	Percent
Branches		9	5	55.56
IF	45	5	3	60.00
IF	70	4	2	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	45	if ((!rst_ni))
-2-:	50	if (endp_qe_i)
-3-:	51	if (ev_qe_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	-	Not Covered
0	-	1	Not Covered
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	73	if (reset_i)
-3-:	78	if (((|((ev_enables & event_i) & (~event_q))) & ep_enabled))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_ctr_out

	Line No.	Total	Covered	Percent
TOTAL		19	15	78.95
ALWAYS	45	7	5	71.43
CONT_ASSIGN	58	1	1	100.00
ALWAYS	70	8	6	75.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
46	1	1
47	1	1
50	1	2
			MISSING_ELSE
51	1	2
			MISSING_ELSE
58	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	0	1
78	1	2
			MISSING_ELSE
80	1	1
84	1	1
85	1	1
86	1	1

---

Cond Coverage for Instance : tb.dut.u_ctr_out

	Total	Covered	Percent
Conditions	4	1	25.00
Logical	4	1	25.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION ((ep_i < 4'(NEndpoints)) ? endpoints[ep_i] : 1'b0)
             -----------1-----------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (((|((ev_enables & event_i) & (~event_q)))) & ep_enabled)
             ---------------------1--------------------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_ctr_out

	Line No.	Total	Covered	Percent
Branches		10	6	60.00
TERNARY	58	1	1	100.00
IF	45	5	3	60.00
IF	70	4	2	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	58	((ep_i < 4'(NEndpoints))) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Covered	T1,T2,T3
0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	45	if ((!rst_ni))
-2-:	50	if (endp_qe_i)
-3-:	51	if (ev_qe_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	-	Covered	T1,T2,T3
0	-	1	Not Covered
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	73	if (reset_i)
-3-:	78	if (((|((ev_enables & event_i) & (~event_q))) & ep_enabled))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_ctr_in

	Line No.	Total	Covered	Percent
TOTAL		19	15	78.95
ALWAYS	45	7	5	71.43
CONT_ASSIGN	58	1	1	100.00
ALWAYS	70	8	6	75.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
46	1	1
47	1	1
50	1	2
			MISSING_ELSE
51	1	2
			MISSING_ELSE
58	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	0	1
78	1	2
			MISSING_ELSE
80	1	1
84	1	1
85	1	1
86	1	1

---

Cond Coverage for Instance : tb.dut.u_ctr_in

	Total	Covered	Percent
Conditions	4	1	25.00
Logical	4	1	25.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION ((ep_i < 4'(NEndpoints)) ? endpoints[ep_i] : 1'b0)
             -----------1-----------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (((|((ev_enables & event_i) & (~event_q)))) & ep_enabled)
             ---------------------1--------------------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_ctr_in

	Line No.	Total	Covered	Percent
Branches		10	6	60.00
TERNARY	58	1	1	100.00
IF	45	5	3	60.00
IF	70	4	2	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	58	((ep_i < 4'(NEndpoints))) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Covered	T1,T2,T3
0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	45	if ((!rst_ni))
-2-:	50	if (endp_qe_i)
-3-:	51	if (ev_qe_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	-	Covered	T1,T2,T3
0	-	1	Not Covered
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	73	if (reset_i)
-3-:	78	if (((|((ev_enables & event_i) & (~event_q))) & ep_enabled))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_ctr_errors

	Line No.	Total	Covered	Percent
TOTAL		19	16	84.21
ALWAYS	45	7	6	85.71
CONT_ASSIGN	61	0	0
CONT_ASSIGN	62	1	1	100.00
ALWAYS	70	8	6	75.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
46	1	1
47	1	1
50	2	2
			==> MISSING_ELSE
51	1	2
			MISSING_ELSE
61		unreachable
62	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	0	1
78	1	2
			MISSING_ELSE
80	1	1
84	1	1
85	1	1
86	1	1

---

Cond Coverage for Instance : tb.dut.u_ctr_errors

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       78
 EXPRESSION (((|((ev_enables & event_i) & (~event_q)))) & ep_enabled)
             ---------------------1--------------------   -----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_ctr_errors

	Line No.	Total	Covered	Percent
Branches		8	5	62.50
IF	45	4	3	75.00
IF	70	4	2	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	45	if ((!rst_ni))
-2-:	50	if (endp_qe_i)
-3-:	51	if (ev_qe_i)

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	-	Excluded		VC_COV_UNR
0	-	1	Not Covered
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	73	if (reset_i)
-3-:	78	if (((|((ev_enables & event_i) & (~event_q))) & ep_enabled))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_ctr_nodata_in

	Line No.	Total	Covered	Percent
TOTAL		19	16	84.21
ALWAYS	45	7	6	85.71
CONT_ASSIGN	58	1	1	100.00
ALWAYS	70	8	6	75.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
46	1	1
47	1	1
50	1	2
			MISSING_ELSE
51	2	2
			==> MISSING_ELSE
58	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	0	1
78	1	2
			MISSING_ELSE
80	1	1
84	1	1
85	1	1
86	1	1

---

Cond Coverage for Instance : tb.dut.u_ctr_nodata_in

	Total	Covered	Percent
Conditions	4	2	50.00
Logical	4	2	50.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION ((ep_i < 4'(NEndpoints)) ? endpoints[ep_i] : 1'b0)
             -----------1-----------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (((|((ev_enables & event_i) & (~event_q)))) & ep_enabled)
             ---------------------1--------------------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_ctr_nodata_in

	Line No.	Total	Covered	Percent
Branches		9	6	66.67
TERNARY	58	1	1	100.00
IF	45	4	3	75.00
IF	70	4	2	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	58	((ep_i < 4'(NEndpoints))) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Covered	T1,T2,T3
0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	45	if ((!rst_ni))
-2-:	50	if (endp_qe_i)
-3-:	51	if (ev_qe_i)

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T2,T3
0	-	0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	73	if (reset_i)
-3-:	78	if (((|((ev_enables & event_i) & (~event_q))) & ep_enabled))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3